Toshiba T3200 User Manual page 176

Pin 1/0 Signal Name
Description
VFO clock. The clock frequency depends on the
data transfer rate.
36 0
$HIFRQ 250 kbps; 8 MHz
300 kbps; 9.6 MHz
500 kbps; 8 MHz
37 0 WINDOW
Window signal generated from the internal
circuit. This signal is active high.
FDD data write clock to the FDC
38 0 WCLK The cycle time of this signal is one-eighth of
CKFDC
Chip select signal to the FDC (U765).
39 0 FDCCS This signal is active (low) when the 1/0 port
address is 3F4HI 3F5H.
40 GND Ground
41 I lOR
1/0 read command.
This signal is active low.
42 I lOW
1/0 write command.
This signal is active low.
FDC reset command. This signal is active high,
43 0 FDSRST
and is issued by the command to 3F2H (data is
D2).
44
I FDCWD
Write data from the FDC
This signal is active high.
Interrupt signal from the FDC
45 I FDCINT This signal is active high, and generates IRQ6
signal.
This signal is to read the status of FDD disk
46 0 XF7RD
change. This signal is active (low) when read
address is 3F7H.
PS 1 and PSO are precompensation control signals.
These signals are output from the FDC
47 I PS1
PSO
PS1 Time
Low Low
No delay
Low
High 225-250 nsdelayed
High Low
225-250 nsquickened
48 I PSO
Precompensation control siqnal.
This signal is to control the VFO operation mode.
49 I SYNC
When this signal is low, it inhibits the read
operation, and when it is high, the read
operation isenabled.
D-5