Toshiba T3200 User Manual page 192

APPENDIX G
PEGA2
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GENERAL
The PEGA2 is a single solution for design of a video
controller.
This chip is composed of 84 pins with 40 multiplexed
bidirectional signals for handling RAM address and data, CPU
address and data, as well as various I/O bits.
Four busses of 8 bits each connect to the four banks of
DRAM, and the fifth 8 bits is used for CPU address and data.
75
84
1
74
12
54
53
32
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