Toshiba T3200 User Manual page 175

Pin I/O Signal Name
Description
This signal is a terminal count signal that
23 I TC
indicates the end of the DMA data transfer.
This signal is active high.
It comes from the DMAC (U8237).
Terminal count signal to the FDC
24 0 FDAKTC
This signal is active high. It is generated from the
TC signal.
25 0
FDACK
DMA acknowledge signal to the FDC
This signal is active low.
DMA cycle request signal from the FDC
26 I
DRQFDC This signal generates DRQ2 to be sent to the
DMAC This signal is active high.
27 I PDS01
Write precompensation ON/ OFF signal.
This signal is fixed to high in this system.
28 Vec + 5V
Interrupt request signal which the FDC outputs at
29
0
IRQ6
the end of command execution.
This signal is active high, and goes to the
U8259A.
This signal inhibits output of the I/O port address
30 I DMACK
during the DMA operation.
When this signal is low, decoding the address is
enabled, and when high, it is disabled.
This is acknowledge signal to DRQ2 which is DMA
31
I DACK2 data transfer request signal.
This signal is active low.
This signal is to switch the printer port connector
to the external FDD.
32
I EXTFDD When this signal is low, the connector is for the
printer port, and when it is high, the connector is
for FDD port.
33
I $16MHZ
Basic clock to the FDC and VFO.
16 M Hz (cycle time is 62.5 ns.)
34 I $19MHZ
Basic clock to the FDC and VFO.
19.2 MHz (cycle time is 52.08 ns.)
FDC clock. Frequency of the clock depends on
the data transfer rate.
35 0 $CKFDC
250 kbps; 8 MHz, 16 MHz
300 kbps; 4.8 MHz, 19.2 MHz
500 kbps' 4 MHz 16 MHz
D-4