Toshiba T3200 User Manual page 153

B.3 SIGNAL DESCRIPTION AND PIN ASSIGNMENT
TABLE B-1 Pin Description
Pin 1/0 Signal Name
Description
CPU hold acknowledge signal.
When this signal is high, the system bus is used by
1 I CPHLDA
any other controller than the CPU.
If this signal is low, the system bus is used by the
CPU.
Memory I/O select signal.
2 I MIO
When this signal is high, memory cycle is being
executed, and when low, I/O cycle.
3 VCC +SV
4 0 SPK Buzzer signal from the external circuit.
Keyboard controller select signal.
S 0 KBCCS
This signal becomes low when the I/O port
address is 062H/ 068H and also KBSEL = 0, or
when the address is 8062"H/ 8068H.
Chip select signal to the BIOS ROM.
This signal is active low.
6 0 LROMCS The address ranges are:
OEOOOOH-OFFFFFH
FEOOOOH-FFFFFFH
Output enable signal to the BIOS ROM.
7 0 ROMOE
This signal is generated by the ROM chip select
signal and memory read command.
This signal is active high.
System bus high enable signal.
8
0 SBHE This signal generates the data bus high enable
signal. This signal is active low.
9
I MEMR Memory read command.
This signal comes from the DMA controller GA
10 I LATAO
and it is generated by SAO.
When this signal is high, the low bank of the
data bus is selected.
Dummy address latch enable signal for the 2nd
11 I CNVALE
byte transfer in 16/8 bit conversion.
This signal also generates output enable signal of
the 1st byte which has been latched.
Address line from the Memory Mapper register
12 0 PGA16
during the DMA cycle or memory refresh cycle.
This signal is used as the system address SA 16
durinQ the slave DMA oQeration.
B-3