Toshiba T3200 User Manual page 171

C • 4
DNA CONTROL
Memory
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DCHGEN
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DCHGDF
lIE
CPUHRQ
DMA
DMHRO
DRQX
I/O
lIE
CPU
CPHLDA
GA
DMHLDA
DMAC
DACKX
Port
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lOR
t I
lOW
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FIGURE C-3 DMA Controller
This circuitry controls the DMA operation.
The DMA GA receives DMHRQ signal from the DMAC, then the GA
responds to the CPU with CPUHRQ signal.
After receiving CPHLDA signal from the CPU, the GA responds
to the DMAC with DMHLDA signal.
The DMAC starts DMA operation when it receives the DMHLDA.
The DMAC prepares the DMA address on the system address bus
and lOR/lOW signal to the DMA GA for the bus control. If
the I/O port is byte oriented device, the bus controller GA
is used for data bus switching (low bank to high bank or
vice versa).
C-ll