Interrupt Wakeup-Enable Register (Iwr) - Motorola DragonBall MC68328 User Manual

MIRQ6 (Mask IRQ6 Interrupt, Bit 19)
This bit, while set, indicates that the external IRQ level-6 interrupt is masked. It is set to 1
after reset.
0 = Enable IRQ6 interrupt
1 = Mask IRQ6 interrupt
MPEN (Mask Pen Interrupt, Bit 20)
This bit, while set, indicates that the pen-down interrupt is masked. It is set to 1 after reset.
0 = Enable pen-down interrupt
1 = Mask pen-down interrupt
MSPIS (Mask SPI Slave Interrupt, Bit 21)
This bit, while set, indicates that the SPI slave interrupt is masked. It is set to 1 after reset.
0 = Enable SPIS interrupt
1 = Mask SPIS interrupt
MTMR1 (Mask Timer 1 Interrupt, Bit 22)
This bit, while set, indicates that the Timer-1 interrupt is masked. It is set to 1 after reset.
0 = Enable timer-1 interrupt
1 = Mask timer-1 interrupt
MIRQ7 (Mask IRQ7 Interrupt, Bit 23)
This bit, while set, indicates that the IRQ7 interrupt is masked. It is set to 1 after reset. The
IRQ7 is nonmaskable in the sense that if the interrupt level is masked all the way to level
7 in the M68000 core, the IRQ7 interrupt is still observed by the processor because the
level 7 interrupt is nonmaskable for the M68000 core. It can, however, be masked by this
control bit.
0 = Enable IRQ7 interrupt
1 = Mask IRQ7 interrupt
2.3.2.5 INTERRUPT WAKEUP-ENABLE REGISTER (IWR). This control register enables
the corresponding interrupt source to start the power-control-wakeup sequence. While the
bit is set, it enables that interrupt to cause wakeup; while the bit is clear, the function is dis-
abled. After reset, all wakeups are enabled and all the bits in this register are set to 1.
2.3.2.6 INTERRUPT STATUS REGISTER (ISR). This register indicates which interrupts
are asserting to the processor. When an interrupt vector is passed to the MC68EC000 core,
the interrupt-handler routine can determine the source of interrupt by examining this status
register. If there are multiple interrupt sources at that level, the software can prioritize them
at that time. There is one interrupt vector for each interrupt level. The lower three bits of the
interrupt vector constitute the interrupt level being acknowledged
MOTOROLA MC68328 DRAGONBALL PROCESSOR USER'S MANUAL
System Integration Module
2-13