Serial Peripheral Interface- Slave (Spis); Overview; Operation - Motorola DragonBall MC68328 User Manual

SECTION 9
SERIAL PERIPHERAL INTERFACE— SLAVE (SPIS)
The slave serial peripheral interface (SPI) operates as an externally clocked slave, allowing
the MC68328 processor to interface with external master devices (for example, POCSAG
paging decoder). The interface is a 3-wire system consisting of the clock, enable, and data-
input pins. It is compatible with SPIs that are popular on Motorola's 68HC05 microcomputer
chips.

9.1 OVERVIEW

The SPI transfers data to the MC68328 processor from a peripheral device over a serial link.
A clock, controlled by the external device, controls transfer. After counting 8 clock cycles,
the shift register data moves to a read buffer, generating an interrupt in the process. Figure
9-1 is a block diagram of the slave SPI.
SPSCLK
SPSEN
SPSRXD

9.2 OPERATION

Users first initialize the SPIS program register. The SPIS then waits for the input-enable
(SPSEN) and clock (SPSCLK) to control the data transfer. The shift register fills with data
over the next 8 clock cycles. On the eighth clock, the shift register contents loads into the
data buffer. The SPISIRQ bit is set, posting an interrupt. The valid data in the buffer awaits
the service routine access.
The clock input performs shifts depending on phase and polarity. In phase 0 mode(PHA=0),
serial data are strobed on the leading edges of SPSCLK. In phase 1 mode(PHA=1), data
are strobed in on trailing edges. The polarity (POL) specifies the inactive state value of
SPSCLK. While POL=1, the idle state of the SPSCLK is high. While POL = 0, the idle state
of the SPSCLK is low. This flexibility allows operation with most serial peripheral devices on
the market.
MOTOROLA
MPU INTERFACE
CONTROL
DATA BUFFER
SHIFT REGISTER
Figure 9-1. SPI Block Diagram
MC68328 DRAGONBALL PROCESSOR USER'S MANUAL
(NOTE: IRQ LEVEL 6
IS GENERATED)
9-1