Signal Descriptions; Spis Register - Motorola DragonBall MC68328 User Manual

SPI-Slave
If enabled, the SPIS operates even if the system clock is inactive. After the SPIS receives a
data byte from an external master, the SPIS interrupt is posted. If the system is in sleep
mode, this interrupt can initiate the wakeup sequence for restoring the system clock. The
SPIS bit (bit 21) in the wakeup control register IWR (at location 0x(FF)FFF308) must be set
for the wakeup sequence to occur.

9.3 SIGNAL DESCRIPTIONS

SPSRXD
This pin is the serial data input to the shift register. A new bit is shifted in on each leading
edge of SPSCLK while in normal mode(POL=0) or on each trailing edge of SPSCLK in
polarity-inverted mode(POL=1). This signal pin is multiplexed with other signals to port K,
bit 4. Refer to Section 7.1.10 for more details.
SPSCLK
This pin is the shift clock input.
SPSEN
This pin indicates that an SPI transfer is in progress. After the enable becomes active, the
SPIS state machine responds to clock edges for data transfer.

9.4 SPIS REGISTER

This register controls the SPIS operation and reports its status. The data register contains
the data transmitted by the external master. After reset, all bits are set to $0000.
9-2 MC68328 DRAGONBALL PROCESSOR USER'S MANUAL
(POL=1, PHA=1)
SPSCLK
(POL=1, PHA=0)
SPSCLK
(POL=0, PHA=1)
SPSCLK
(POL=0, PHA=0)
SPSCLK
SPSEN
SPSRXD
B7
Figure 9-2. SPIS Operation
B6 B5 B4 B3 B2 B1 B0
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