Pll Operation; Initial Powerup; Divider - Motorola DragonBall MC68328 User Manual

the frequency. Another bit prepares for the VCO frequency change. While this register can
be accessed as bytes, it should always be written as a 16-bit word.
15 14 13 12
CLK32 PROT UNUSED
Address: $(FF)FFF202
CLK32 Clock 32
This bit indicates the current status of the CLK32 signal and synchronizes the software to
the 32kHz reference clock when the VCO frequency is to be changed or the PLL is to be
disabled. Refer to Section 3.3 PLL Operation for details.
PROT Protect Bit
This bit protects the "P" and "Q" counter values from additional writes. After this bit is set
by software, the frequency-select register cannot be written. Only a reset clears this bit.
QC Q Count
These bits control the "Q" counter.
PC P Count
These bits control the "P" counter.

3.3 PLL OPERATION

This section describes the operation and preferred sequences to control the PLL.

3.3.1 Initial Powerup

At initial powerup, the crystal oscillator begins oscillation within several hundred millisec-
onds. While reset remains asserted, the PLL begins the lockup sequence and locks within
several milliseconds of the crystal oscillator startup. Once lockup occurs, the system clock
is available at the default master frequency of 16.580608 MHz (assuming a 32.768 kHz crys-
tal). To generate the master frequency, multiply the reference (32.768 kHz) by the PLL divi-
sor. The default divisor is 506. The divisor can be changed under software control and is
outlined below.
The default divider value (506) was selected as it can directly
generate standard baud frequencies at accuracies of better than
0.01%.

3.3.2 Divider

The PLL uses a dual-modulus prescaler to reduce power consumption. This approach
divides the VCO frequency by 14 before it is fed to the rest of the divider chain. Dual-mod-
ulus counters operate differently from other counters in that the overall divide ratio is depen-
dent on two separate values, P and Q. Besides the power-saving advantage above a divisor
MOTOROLA MC68328 DRAGONBALL PROCESSOR USER'S MANUAL
11 10 9 8
QC
Figure 3-3. Frequency-Select Register
NOTE
Phase-Locked Loop and Power Control
7 6 5 4
PC
3 2 1 0
Reset Value: $0123
3-3