Motorola DragonBall MC68328 User Manual page 35

System Integration Module
POL2 Polarity Control for Interrupt 2
0 = Negative polarity
1 = Positive polarity
POL3 Polarity Control for Interrupt 3
0 = Negative polarity
1 = Positive polarity
POL6 Polarity Control for Interrupt 6
0 = Negative polarity
1 = Positive polarity
2.3.2.4 INTERRUPT MASK REGISTER (IMR). This control register masks the interrupt if
the corresponding control bit is set. There is one control bit for each interrupt source. When
an interrupt is masked, it does not generate an interrupt request to the processor core, but
its status can still be observed in the interrupt-pending register. From reset, all the interrupts
are masked and all the bits in this register are set to 1.
The interrupt-mask bit positions corresponds to the bits in the interrupt-status register, inter-
rupt-pending register, and wakeup-enable register. When each bit is set, its interrupt is
masked (disabled).
MSPIM (Mask SPI Master Interrupt, Bit 0)
This bit, while set, indicates that the SPI master interrupt is masked. It is set to 1 after re-
set.
0 = Enable SPI master interrupt
1 = Mask SPI master interrupt
MTMR2 (Mask Timer 2 Interrupt, Bit1)
This bit, while set, indicates that the timer-2 interrupt is masked. It is set to 1 after reset.
0 = Enable timer-2 master interrupt
1 = Mask timer-2 master interrupt
MUART (Mask UART Interrupt, Bit2)
This bit, while set, indicates that the UART interrupt is masked. It is set to 1 after reset.
0 = Enable UART interrupt
1 = Mask UART interrupt
MWDT (Mask Watchdog Timer Interrupt, Bit 3)
This bit, while set, indicates that the watchdog timer interrupt is masked. It is set to 1 after
reset.
0 = Enable WDT interrupt
1 = Mask WDT interrupt
2-10 MC68328 DRAGONBALL PROCESSOR USER'S MANUAL MOTOROLA