Spim Registers; Spim Control/Status Register - Motorola DragonBall MC68328 User Manual

SPMTxD Transmit Data
This pin is the shift-register output. A new data bit is presented on each rising edge of the
SPMCLK in normal mode or on each falling edge of SPMCLK in inverted mode.
SPMRxD Receive Data
This pin is the shift-register input. A new bit is shifted in on each falling edge of SPMCLK
while in normal mode or on each rising edge of SPMCLK in inverted mode.
SPMCLK Shift Clock
This pin is the clock output. When the SPIM is enabled, a selectable number of clock puls-
es is issued. While POL = 0, this signal is low while the SPIM is idle. When POL = 1, this
signal is high during idle.

10.4 SPIM REGISTERS

These registers control the SPIM operation and report its status. The data register
exchanges data with external slave devices. After reset, all bits are set to $0000.

10.4.1 SPIM Control/Status Register

This register controls the SPIM operation and reports its status.
15 14 13 12
DATA RATE RESVD RESVD RESVD SPMEN
Address: (FF)FFF802
DATA RATE
These bits select the baud rate of the SPMCLK based of divisions of the system clock.
The master clock for the SPIM is SYSCLK. The bits are encoded as:
000 = Divide by 4
001 = Divide by 8
010 = Divide by 16
011 = Divide by 32
100 = Divide by 64
101 = Divide by 128
110 = Divide by 256
111 = Divide by 512
SPMEN
This bit enables the SPIM. The enable should be asserted before initiating an exchange
and should be negated after the exchange is complete.
0 = SPI master disable
1 = SPI master enable
MOTOROLA MC68328 DRAGONBALL PROCESSOR USER'S MANUAL
11 10 9 8
XCH
Figure 10-3. SPIM Control/Status Register
7 6 5 4
SPMIRQ IRQEN PHA POL
SPI-Master
3 2 1 0
BIT COUNT
Reset Value: $0000
10-3