Motorola DragonBall MC68328 User Manual page 125

SPI-Master
XCH
This bit triggers the state machine to generate (n= clock count) clocks at the selected bit
rate. After the n-bit transfer, new data may be loaded and another exchange initiated. At
least 2 SPI clocks should elapse before re-enabling this bit. This bit clears automatically.
1 = Initiate exchange
0 = SPI is idle or exchange in progress
To ensure a complete exchange, users should check the SPI-
MIRQ bit rather than XCH bit. The IRQEN should be on. Users
not wanting to receive interrupt upon completion of exchange
can disable the incoming SPIM interrupt by masking it in the IMR
in the interrupt controller.
SPIMIRQ
An interrupt is asserted at the end of an exchange (assuming IRQEN is enabled). This bit
is asserted until users clear it by writing a 0. Users can write these bits to generate an IRQ
on demand.
0 = No interrupt posted
1 = Interrupt posted
IRQEN
This bit will enable the SPIM interrupt. This bit is cleared to 0 on reset and must be en-
abled by software.
0 = Interrupts disabled
1 = Interrupts enabled
PHA
This bit controls the SPMCLK phase shift.
0 = Normal phase
1 = Shift advance to opposite phase
POL
This bit controls the SPMCLK polarity.
0 = Active-high polarity (0=idle)
1 = Inverted polarity (1= idle)
CLOCK COUNT
These bits select the transfer length (up to 16 bits can be transferred).
0000 = 1 bit transfer
1111 = 16 bit transfer
10-4 MC68328 DRAGONBALL PROCESSOR USER'S MANUAL
NOTE
MOTOROLA