Power Control Module Overview; Description - Motorola DragonBall MC68328 User Manual

ware to the rising edge of CLK32, write the disable bit, then execute a STOP instruction. The
CPU no longer fetches instructions then waits for the clock to stop. When an interrupt awak-
ens the system after the PLL acquires lock, the CPU executes an interrupt-service routine
for the level of the pending interrupt. After the interrupt-service routine, the CPU begins exe-
cution at the instruction after the STOP instruction. The instruction sequence below illus-
trates the flow. It is assumed that all peripherals and the LCD controller have been shut
down before the PLL stops.
WAIT
* The system waits here for the PLL to restart after a wakeup IRQ
* After the IRQ routine, the instruction flow continues from here

3.4 POWER CONTROL MODULE OVERVIEW

The power control module improves power efficiency as it allocates power (clocks) to the
CPU core and other modules in the MC68328 processor under software control. Clocks can
be enabled in bursts. While executing tasks that require significant CPU resources, the clock
can be enabled for extended periods of time. While the CPU is relatively idle, the clock can
be disabled or bursted with a low duty cycle. When a wakeup interrupt occurs, the clock is
immediately enabled, allowing the CPU to service the request. The DMA controller is not
affected by the power controller. It has full access to the bus while the CPU is idle, keeping
the screen refreshed. The following sections describe the use and operation of the power
control block.

3.4.1 Description

Figure 3-4 is a block diagram of the power control module. Following reset, the power con-
troller is disabled and the MC68EC000 clock is continuously on. When the block is enabled,
software controls the clock burst width in increments of 1/31. Initially, the duty cycle is set to
100%. Software can then change the duty cycle to a lower value and the clock begins to
burst. In normal operation, the MC68EC000 does not have to operate continuously. Usually,
it waits for user input. An interrupt from the keyboard, for example, disables the power con-
troller, and the clock again becomes continuous. When the software completes its service
of the task, the power controller can again be enabled to burst the clock and reduce power
consumption. Clock control is in increments of approximately 3% (1/31).
When the burst-width control sub-block indicates that the CPU clock's time slot has expired
and is to be disabled, clock control requests the bus from the CPU. After the bus is granted,
the clock stops. Bus grant to the DMA controller is asserted and the DMA controller has
complete access to the bus.
If a wakeup interrupt event occurs while the CPU clock is disabled, the clock is immediately
enabled and the CPU processes the interrupt. The DMA controller always has priority, so if
MOTOROLA MC68328 DRAGONBALL PROCESSOR USER'S MANUAL
lea #$FFF202, AO
move.w (A0),D0
bpl.w WAIT
bset #3,(A0)
stop #$2000
JMP STARTUP
Phase-Locked Loop and Power Control
point to the Freq Sel Register
synchronize to rising CLK32 edge
wait for CLK32 to go high
Disable the PLL
stop fetching and wait for any IRQ
jump to housekeeping routine
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