Motorola DragonBall MC68328 User Manual page 29

System Integration Module
Group Base Register
ADDR
UDS
LDS
R/W
AS
Group Mask Register
DTACK
The default for each chip-select is a 16-bit data-bus width. The BUSW bits in the chip-select
option registers enable 16-bit/8-bit data-bus width for each of the 16 chip-select ranges. The
initial bus width for the boot chip-select is selected by placing on the BBUSW pin at reset a
logic 0 or 1 to specify 8-bit or 16-bit wide data bus, respectively. This allows a boot EPROM
of either data-bus width to be used in any given system.
All external accesses that do not match one of the chip-select address ranges will be
assumed to be a 16-bit device. That is just one access performed for a 16-bit transfer. It can
also be a 8-bit port but accessed at every other byte.
The boot chip-select is initialized from cold reset to assert in response to any address except
the on-chip module register space (i.e. $FFFFF000 to $FFFFFFFF or $FFF000 to
$FFFFFF). This ensures a chip-select to the boot ROM or EPROM to fetch the reset vector
and execute the initialization code, which should set up the SCR and the chip-select ranges
early on in that initialization sequence.
The data-bus port size for CSA0 on reset, and hence the data width of the boot ROM device,
is programmed by placing on the BBUSW pin during reset logic 0 or 1 for 8-bit and 16-bit
wide data bus, respectively.
The other chip-selects are initialized to be nonvalid, and so will not assert until they are pro-
grammed and the valid bits set.
2-4 MC68328 DRAGONBALL PROCESSOR USER'S MANUAL
Compare Logic
CSA
CSB
CSC
CSD
DTACK Generation
CSD3 Compare Logic
PCMCIA V1.0
Figure 2-2. Chip Select Block
Chip-Select Base Register
Compare Logic
Chip-Select Mask Register
CSA0
CSA1
CSA2
CSA3
CE1
CE2
OE
WE
CSA0-CSA3
CSB0-CSB3
CSC0-CSC3
CSD0-CSD3
MOTOROLA