Sub-Block Description; Transmitter - Motorola DragonBall MC68328 User Manual

(3) can serve as the source of the clock to the baud-rate generator, and (4) can output the
bit clock at the selected baud rate.

8.2 SUB-BLOCK DESCRIPTION

The UART module is easy to use from both a hardware and software perspective. Five work-
ing registers provide all status and control functions. The registers are optimized for a 16-bit
bus. For example, all status bits associated with the received data are available along with
the data byte in a single 16-bit read. All register bits are readable and most are read/write.
The modem-control signals are flexible. CTS is an input that can provide hardware flow-con-
trol to the transmitter, or it can serve as a general-purpose input. A maskable interrupt is
posted on each transition of this signal. RTS is an output from the receiver that indicates that
the receiver has room in the FIFO for data. This bit can be configured as a general-purpose
output. A GPIO pin is provided that can bring an external bit-clock into the module. It can
also serve as a general-purpose input with a maskable interrupt posted on each transition.
It can be configured as an output that provides a bit-clock or a signal under software control.
The UART consists of four submodules. This section briefly describes the basic functionality
of the 4 blocks.

8.2.1 Transmitter

The transmitter accepts a character (byte) from the MPU bus and transmits it serially. While
the FIFO is empty, the transmitter outputs continuous IDLE (1 while in NRZ, 0 while in IrDA
mode). When a character is available for transmission, the start, stop, and parity (if enabled)
bits are added to the character and it is serially shifted at the selected bit rate. The transmit-
ter posts a maskable interrupt when it needs parallel data. Three interrupts are available. If
users want to take full advantage of the 8-byte FIFO, the FIFO EMPTY interrupt should be
enabled. In the interrupt-service routine, the FIFO should be interrogated after each byte is
loaded. If space is available (the TX AVAIL bit is set), more data will be loaded into the FIFO.
The transmitter will not generate another interrupt until the FIFO has completely emptied. If
working with software that has a large interrupt-service latency, use the FIFO HALF inter-
rupt. In this case, the transmitter generates an interrupt when the FIFO occupancy is less
than 4 bytes. If the FIFO is not needed, use the TX AVAIL interrupt. An interrupt will be gen-
erated whenever at least one space is available in the FIFO.
CTS can control the serial data flow. If CTS is negated (high), the transmitter finishes send-
ing the character in progress (if any), then waits for CTS to again become asserted (low).
Set the SEND BREAK bit in the transmitter register to generate a BREAK character (contin-
uous 0's). Users' software must know the baud rate. The SEND BREAK bit must be asserted
for a sufficient time to generate a valid BREAK character. Users can generate parity errors
for debugging purposes. The transmitter operates from the 1x clock provided by the baud-
rate generator.
While the infrared interface is enabled, the transmitter produces a pulse that is 3/16 of a bit
time for each 0 bit sent. The TXD port can directly drive an infrared LED or directly interface
with popular IrDA transceivers.
MOTOROLA MC68328 DRAGONBALL PROCESSOR USER'S MANUAL
UART
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