Intel Xeon Processor E5-1600 Datasheet
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Intel Xeon Processor E5-1600 Datasheet

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Intel® Xeon® Processor E5-1600/
E5-2600/E5-4600 Product Families
Datasheet - Volume One
May 2012
Reference Number: 326508, Revision: 002

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  • Page 1 Intel® Xeon® Processor E5-1600/ E5-2600/E5-4600 Product Families Datasheet - Volume One May 2012 Reference Number: 326508, Revision: 002...
  • Page 2 SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS OTHERWISE AGREED IN WRITING BY INTEL, THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR.

  • Page 3: Table Of Contents

    Intel Virtualization Technology Processor Extensions ........81 Security Technologies ..................81 3.2.1 Intel® Trusted Execution Technology............81 3.2.2 Intel Trusted Execution Technology – Server Extensions ......82 3.2.3 Intel® Advanced Encryption Standard Instructions (Intel® AES-NI)....82 Intel® Xeon® Processor E5-1600/ E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 4 Intel® Turbo Boost Technology ................83 3.4.1 Intel® Turbo Boost Operating Frequency ...........83 Enhanced Intel SpeedStep® Technology ...............84 Intel® Intelligent Power Technology..............84 Intel® Advanced Vector Extensions (Intel® AVX) ..........84 Intel Dynamic Power Technology .................85 Power Management ....................87 ACPI States Supported ..................87 4.1.1 System States..................87...
  • Page 5 Signal Quality ....................181 7.10.1 DDR3 Signal Quality Specifications ............182 7.10.2 I/O Signal Quality Specifications............. 182 7.10.3 Intel QuickPath Interconnect Signal Quality Specifications......182 7.10.4 Input Reference Clock Signal Quality Specifications........182 7.10.5 Overshoot/Undershoot Tolerance............182 Processor Land Listing................... 187 Listing by Land Name ..................
  • Page 6 Figures Intel® Xeon® Processor E5-2600 Product Family on the 2 Socket Platform ......................14 PCI Express* Lane Partitioning and Direct Media Interface Gen 2 (DMI2)....17 PCI Express* Layering Diagram ................26 Packet Flow through the Layers ................27 Ping() ......................32 Ping() Example....................32 GetDIB() ......................32 Device Info Field Definition .................33...
  • Page 7 7-11 Maximum Acceptable Overshoot/Undershoot Waveform........185 Processor Package Assembly Sketch ..............237 Processor Package Drawing Sheet 1 of 2 ............239 Processor Package Drawing Sheet 2 of 2 ............240 Processor Top-Side Markings ................242 Intel® Xeon® Processor E5-1600/ E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 8 System Memory Power States ................88 DMI2/PCI Express* Link States................89 Intel QPI States....................89 G, S and C State Combinations................90 P_LVLx to MWAIT Conversion ................92 Coordination of Core Power States at the Package Level..........95 Intel® Xeon® Processor E5-1600/ E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 9 PCI Express* Port 3 Signals ................143 PCI Express* Miscellaneous Signals ..............143 DMI2 and PCI Express* Port 0 Signals..............144 Intel QPI Port 0 and 1 Signals ................144 Intel QPI Miscellaneous Signals ................. 144 6-10 PECI Signals ....................145 6-11 System Reference Clock (BCLK{0/1}) Signals .............
  • Page 10 10-1 PWM Fan Frequency Specifications For 4-Pin Active Thermal Solution...... 254 10-2 8 Core / 6 Core Server Thermal Solution Boundary Conditions ....... 256 10-3 4 Core Server Thermal Solution Boundary Conditions ........... 256 Intel® Xeon® Processor E5-1600/ E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 11: Revision History

    Revision History Revision Description Revision Date Number Initial Release March 2012 Added Intel® Xeon® Processor E5-4600 Product Family May 2012 § Intel® Xeon® Processor E5-1600/ E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 12 Intel® Xeon® Processor E5-1600/ E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 13: Overview

    Throughout this document, the Intel® Xeon® processor E5-1600/E5- 2600/E5-4600 product families may be referred to as simply the processor. Where information differs between the EP and EP 4S SKUs, this document uses specific Intel® Xeon® processor E5-1600 product family, Intel® Xeon® processor E5-2600 product family, and Intel®...

  • Page 14: Processor Feature Details

    Intel® Xeon® Processor E5-4600 Product Family on the 4 Socket Platform 1.1.1 Processor Feature Details • Up to 8 execution cores • Each core supports two threads (Intel® Hyper-Threading Technology), up to 16 threads per socket Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 15: Supported Technologies

    • Up to 20 MB last level cache (LLC): up to 2.5 MB per core instruction/data last level cache (LLC), shared among all cores • The Intel® Xeon® processor E5-4600 product family supports Directory Mode, Route Through, and Node IDs to reduce unnecessary Intel QuickPath Interconnect traffic by tracking cache lines present in remote sockets.

  • Page 16: Pci Express

    ECC (with or without data scrambler) or a predefined test pattern • Isochronous access support for Quality of Service (QoS), native 1 and 2 socket platforms - Intel® Xeon® processor E5-1600 and E5-2600 product families only • Minimum memory configuration: independent channel support with 1 DIMM populated •...
  • Page 17 • Supports receiving and decoding 64 bits of address from PCI Express*. — Memory transactions received from PCI Express* that go above the top of physical address space (when Intel VT-d is enabled, the check would be against the translated HPA (Host Physical Address) address) are reported as errors by the processor.

  • Page 18: Direct Media Interface Gen 2 (Dmi2)

    • Transparent to software • Processor and peer-to-peer writes and reads with 64-bit address support • APIC and Message Signaled Interrupt (MSI) support. Will send Intel-defined “End of Interrupt” broadcast message when initiated by the processor. • System Management Interrupt (SMI), SCI, and SERR error indication •...

  • Page 19: Platform Environment Control Interface (Peci)

    — Reference Clock is 100 MHz — Slow boot speed initialization at 50 MT/s • Common reference clocking (same clock generator for both sender and receiver) • Intel® Interconnect Built-In-Self-Test (Intel® IBIST) for high-speed testability • Polarity and Lane reversal (Rx side only) 1.2.5...

  • Page 20: Pci Express

    Third generation Double Data Rate SDRAM memory technology that is the successor to DDR2 SDRAM Direct Memory Access Direct Media Interface DMI2 Direct Media Interface Gen 2 Digital Thermal Sensor Error Correction Code Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 21 See the Intel® 64 and IA-32 Architectures Software Developer's Manuals for more detailed information. Flit Flow Control Unit. The Intel QPI Link layer’s unit of transfer; 1 Flit = 80-bits. Functional Operation Refers to the normal operating conditions in which all processor specifications, including DC, AC, system bus, signal quality, mechanical, and thermal, are satisfied.
  • Page 22 PCI Express* Generation 2.0/3.0 PECI Platform Environment Control Interface Phit Physical Unit. An Intel® QPI terminology defining units of transfer at the physical layer. 1 Phit is equal to 20 bits in ‘full width mode’ and 10 bits in ‘half width mode’ Processor...

  • Page 23: Related Documents

    Refer to the following documents for additional information. Table 1-1. Referenced Documents (Sheet 1 of 2) Document Location Intel® Xeon® Processor E5 Product Family Datasheet Volume Two http://www.intel.com Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families http://www.intel.com Thermal/Mechanical Design Guide Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families http://www.intel.com...

  • Page 24: State Of Data

    Overview Table 1-1. Referenced Documents (Sheet 2 of 2) Document Location Intel® Virtualization Technology Specification for Directed I/O http://download.intel.com/technolog Architecture Specification y/computing/vptech/Intel(r)_VT_for_ Direct_IO.pdf Intel® Trusted Execution Technology Software Development Guide http://www.intel.com/technology/sec urity/ State of Data The data contained within this document is the most accurate information available by the publication date of this document.

  • Page 25: Interfaces

    The type of memory supported by the processor is dependent on the target platform: • Intel® Xeon® processor E5 product family-based platforms support: — ECC registered DIMMs: with a maximum of three DIMMs per channel allowing up to eight device ranks per channel.

  • Page 26: Pci Express* Interface

    Physical Layer representation to the Data Link Layer representation and finally (for Transaction Layer Packets) to the form that can be processed by the Transaction Layer of the receiving device. Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 27: Pci Express* Configuration Mechanism

    PCI Express* extends the configuration space to 4096 bytes per-device/function, as compared to 256 bytes allowed by the Conventional PCI Specification. PCI Express* configuration space is divided into a PCI-compatible region (which consists of the first Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 28: Dmi2/Pci Express* Interface

    Intel QuickPath Interconnect The Intel QuickPath Interconnect is a high speed, packetized, point-to-point interconnect used in the 2nd Generation Intel(r) Core(TM) Processor Family. The narrow high-speed links stitch together processors in distributed shared memory and integrated I/O platform architecture. It offers much higher bandwidth with low latency.
  • Page 29 • The Protocol layer is the high-level set of rules for exchanging packets of data between devices. A packet is comprised of an integral number of Flits. The Intel QuickPath Interconnect includes a cache coherency protocol to keep the distributed memory and caching structures coherent during system operation. It supports both low-latency source snooping and a scalable home snoop behavior.

  • Page 30: Platform Environment Control Interface (Peci)

    • Synchronization at the beginning of every message minimizes device timing accuracy requirements Note: The PECI commands described in this document apply primarily to the Intel® Xeon® processor E5-1600/E5-2600/E5-4600 product families. The processors utilizes the capabilities described in this document to indicate support for four memory channels.

  • Page 31: Client Command Suite

    2.5.1.3 Processor Interface Tuning and Diagnostics The processor Intel® Interconnect Built In Self Test (Intel® IBIST) allows for in-field diagnostic capabilities in the Intel® QPI and memory controller interfaces. PECI provides a port to execute these diagnostics via its PCI Configuration read and write capabilities in the BMC INIT mode.

  • Page 32: Ping() Example

    Read Length: 0x08 Command: 0xf7 Figure 2-5. GetDIB() Byte # Write Length Read Length Cmd Code Client Address Byte 0x01 0x08 0xf7 Definition Revision Device Info Reserved Reserved Reserved Number Reserved Reserved Reserved Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 33: Device Info Field Definition

    Ping(), GetDIB(), GetTemp() Ping(), GetDIB(), GetTemp(), WrPkgConfig(), RdPkgConfig() Ping(), GetDIB(), GetTemp(), WrPkgConfig(), RdPkgConfig(), RdIAMSR() Ping(), GetDIB(), GetTemp(), WrPkgConfig(), RdPkgConfig(), RdIAMSR(), RdPCIConfigLocal(), WrPCIConfigLocal() Ping(), GetDIB(), GetTemp(), WrPkgConfig(), RdPkgConfig(), RdIAMSR(), RdPCIConfigLocal(), WrPCIConfigLocal(), RdPCIConfig() Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 34: Gettemp()

    Section 2.5.2.4 or using a RDMSR instruction. T application to fan speed control management is defined in CONTROL the Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/ Mechanical Design Guide. Please refer to Section 2.5.7 for details regarding PECI temperature data formatting.

  • Page 35: Gettemp() Example

    ‘parameter’ field to specify the exact data being requested. The Read Length dictates the desired data return size. This command supports only dword responses on the Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 36: Rdpkgconfig() Response Definition

    Refer to Section 2.5.2.6 for more details on processor-specific services supported through this command. 2.5.2.5.1 Command Format The WrPkgConfig() format is as follows: Write Length: 0x0a(dword) Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 37: Wrpkgconfig() Response Definition

    WrPkgConfig() Response Definition (Sheet 1 of 2) Response Meaning Bad Write FCS Electrical error or AW FCS failure Abort FCS Illegal command formatting (mismatched RL/WL/Command Code) CC: 0x40 Command passed, data is valid. Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 38 The user should consult the Intel® 64 and IA-32 Architectures Software Developer’s Manual (SDM) Volumes 1, 2, and 3 or Intel® Xeon® Processor E5 Product Family Datasheet Volume Two for details on MSR and CSR register contents.

  • Page 39: Rdpkgconfig() & Wrpkgconfig() Dram Thermal And Power Optimization Services Summary

    DRAM Power Read DRAM Maximum DRAM MSR 61Ch: Info Read power settings power settings & DRAM_POWER_INFO 0x0000 info to be used maximum time by power CSR: DRAM_POWER_INFO window limiting entity Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 40: Dram Thermal Estimation Configuration Data

    The ‘Scaling Factor’ is used to convert memory transaction information to energy units in Joules and can be derived from system/memory configuration information. Refer to the Intel® 64 and IA-32 Architectures Software Developer’s Manual (SDM) Volumes 1, 2, and 3 for methods to program and access ‘Scaling Factor’...

  • Page 41: Dram Rank Temperature Write Data

    TSOD or on-board DIMM sensor and requires that CLTT (closed loop throttling mode) be enabled and OLTT (open loop throttling mode) be disabled. Refer to Table 2-7 for channel index encodings. Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 42: The Processor Dimm Temperature Read / Write

    This would include all the DIMMs within the channel and all the ranks within each of the DIMMs. Channels that are not populated will return the ‘ambient temperature’ on systems using activity-based temperature estimations or alternatively return a ‘zero’ for systems using sensor-based temperatures. Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 43: Processor Dram Channel Temperature

    Table 2-7. A channel index of 0x00FF is used to specify the “all channels” case. While Intel requires reading the accumulated energy data at least once every 16 seconds to ensure functional correctness, a more realistic polling rate recommendation is once every 100 mS for better accuracy. This feature assumes a 200W memory capacity.

  • Page 44: Dram Power Info Read Data

    RST_CPL bit of the BIOS_RESET_CPL register. The DRAM power settings will be programmed during boot independent of the ‘DRAM Power Limit Enable’ bit setting. Please refer to the Intel® Xeon® Processor E5 Product Family Datasheet Volume Two for information on memory energy estimation methods and energy tuning options used by BIOS and other utilities for determining the range specified in the DRAM power settings.

  • Page 45: Dram Power Limit Data

    Figure 2-20. DRAM Power Limit Performance Data Accumulated DRAM Throttle Time DRAM Power Limit Performance Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 46: Rdpkgconfig() & Wrpkgconfig() Cpu Thermal And Power Optimization Services Summary

    The user should consult the appropriate Intel® 64 and IA-32 Architectures Software Developer’s Manual (SDM) Volumes 1, 2, and 3 or Intel® Xeon® Processor E5 Product Family Datasheet Volume Two for exact details on MSR or CSR register content.
  • Page 47 PACKAGE_ENERGY_STATUS package. CSR: PACKAG_ENERGY_STATUS Power Limit for MSR 638h: PP0_POWER_LIMIT the VCC Power Program power limit 0x0000 Power Limit Data Plane Write / for VCC power plane CSR: PP0_POWER_LIMIT Read Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 48 Read Mode associated valid that IERR was caused by a core timeout Thermal margin Read margin to Thermal Margin to processor 0x0000 processor thermal Read thermal profile load line or load line Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 49: Cpuid Data

    Processor Flag[2:0] as shown in Figure 2-22 is typically unique to the platform type and processor stepping. Refer to the Intel® 64 and IA-32 Architectures Software Developer’s Manual (SDM) Volumes 1, 2, and 3 for more information. Figure 2-22. Platform ID Data...

  • Page 50: Maximum Thread Id

    [12:8] is 10000b and the time unit [19:16] is 1010b. Actual unit values are calculated as shown in Table 2-9. Figure 2-27. Package Power SKU Unit Data 16 15 Reserved Time Unit Reserved Energy Unit Reserved Power Unit Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 51: Power Control Register Unit Calculations

    PCU enough time to sample energy information and enforce the limit. The minimum value of the ‘time window’ can be obtained by reading bits [21:15] of the PWR_LIMIT_MISC_INFO CSR using the PECI RdPCIConfigLocal() command. Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 52: Package Power Sku Data

    ‘instantaneous’ value and not the ‘average’ value as returned by the PECI GetTemp() described in Section 2.5.2.3. Figure 2-29. Package Temperature Read Data Sign PECI Temperature PECI Temperature RESERVED (Integer Value) (Fractional Value) Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 53: Temperature Target Read

    A bit set to ‘1’ is ignored and results in no change to any sticky log bits. For example, to clear the TCC Activation Log bit and retain all other log bits, the Thermal Status Read should send a mask of 0xFFFFFFFD. Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 54: Thermal Status Word

    Actual current limit data is contained only in the lower 13 bits of the response data. The default return value of 0x438 corresponds to a current limit value of 135A. Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 55: Current Config Limit Read Data

    Section 2.5.2.6.13. While Intel requires reading the accumulated energy data at least once every 16 seconds to ensure functional correctness, a more realistic polling rate recommendation is once every 100mS for better accuracy. This feature assumes a 150W processor. In general, as the power capability decreases, so will the minimum polling rate requirement.

  • Page 56: Power Limit Data For Vcc Power Plane

    PECI. Intel recommends exclusive use of just one entity or interface, PECI for instance, to manage all processor package power limiting and budgeting needs. If PECI is being...

  • Page 57: Package Turbo Power Limit Data

    32-bit counter that wraps around. The unit for time is determined as per the Package Power SKU Unit settings described in Section 2.5.2.6.13. Figure 2-37. Package Power Limit Performance Data Accumulated CPU Throttle Time Accumulated CPU Throttle Time Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 58: Efficient Performance Indicator Read

    Any power management entity monitoring this indicator should sample it at least once every 4 seconds to enable detection of wraparounds. Refer to the processor Intel® 64 and IA-32 Architectures Software Developer’s Manual (SDM) Volumes 1, 2, and 3, for details on programming the Energy/Performance Bias (MSR_MISC_PWR_MGMT) register to set the ‘Energy Efficiency’...

  • Page 59: Caching Agent Tor Read Data

    This PECI service will continue to return valid margin values even when the processor die temperature exceeds T jmax Figure 2-41. DTS Thermal Margin Read Sign Thermal Margin Therm al Margin RESERVED (Integer Value) (Fractional Value) Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 60 RdIAMSR() The RdIAMSR() PECI command provides read access to Model Specific Registers (MSRs) defined in the processor’s Intel® Architecture (IA). MSR definitions may be found in the Intel® 64 and IA-32 Architectures Software Developer’s Manual (SDM) Volumes 1, 2, and 3. Refer to...
  • Page 61 Thread (0,1) Mask for Core4 Figure 2-43. RdIAMSR() Note: The 2-byte MSR Address field and read data field defined in Figure 2-43 are sent in standard PECI ordering with LSB first and MSB last. Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 62: Rdiamsr() Response Definition

    IA32_MCG_CAP[7:0] MSR (0x0179). This register may be alternatively read using a RDMSR BIOS instruction. Please consult the Intel® 64 and IA-32 Architectures Software Developer’s Manual (SDM) Volumes 1, 2, and 3 for more information on the exact number of cores supported by a particular processor SKU.
  • Page 63 10. Reads to a machine check bank within a core or thread that is disabled will return all zeroes with a completion code of 0x90. 11. For SKUs where Intel QPI is disabled or absent, reads to the corresponding machine check banks will return all zeros with a completion code of 0x40.

  • Page 64: Pci Configuration Address

    Actual PCI bus numbers for all PCI devices including the PCH are programmable by BIOS. The bus number for PCH devices may be obtained by reading the CPUBUSNO CSR. Refer to the Intel® Xeon® Processor E5 Product Family Datasheet Volume Two document for details on this register.

  • Page 65: Pci Configuration Address For Local Accesses

    The RdPCIConfigLocal() command provides sideband read access to the PCI configuration space that resides within the processor. This includes all processor IIO and uncore registers within the PCI configuration space as described in the Intel® Xeon® Processor E5 Product Family Datasheet Volume Two document.

  • Page 66: Rdpciconfiglocal() Response Definition

    Response timeout. The processor was not able to generate the required response in a timely fashion. Retry is appropriate. CC: 0x81 Response timeout. The processor is not able to allocate resources for servicing this command at this time. Retry is appropriate. Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 67 Description: Writes the data sent to the requested register address. Write Length dictates the desired write granularity. The command always returns a completion code indicating pass/fail status. Refer to Section 2.5.5.2 for details on completion codes. Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 68: Wrpciconfiglocal() Response Definition

    Retry may be appropriate after modification of PECI wake mode behavior if appropriate. CC: 0x90 Unknown/Invalid/Illegal Request CC: 0x91 PECI control hardware, firmware or associated logic error. The processor is unable to process the request. Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 69: Client Management

    IIO functions as described in Table 2-15. Refer to the Intel® Xeon® Processor E5 Product Family Datasheet Volume Two for more details on specific register definitions. It also enables writing to processor REUT (Robust Electrical Unified Test) registers associated with the Intel QPI, PCIe* and DDR3 functions.

  • Page 70: The Processor Peci Power-Up Timeline()

    2-17. These package strap(s) are evaluated at the assertion of PWRGOOD (as depicted in Figure 2-49). Refer to the appropriate Platform Design Guide (PDG) for recommended resistor values for establishing non-default SOCKET_ID settings. Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 71: Socket Id Strapping

    Not measurable. PECI client will not return valid data in core C-state that is C3 or deeper RdPCIConfigLocal() May require package ‘pop-up’ to C2 state WrPCIConfigLocal() May require package ‘pop-up’ to C2 state RdPCIConfig() May require package ‘pop-up’ to C2 state Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 72 BMC. In this mode, the socket performs a minimal amount of internal configuration and then waits for the BMC or service processor to complete the initialization. Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 73 2.5.3.7.2 Link Init Mode In cases where the socket is not one Intel QPI hop away from the Firmware Agent socket, or a working link to the Firmware Agent socket cannot be resolved, the socket is placed in Link Init mode. The socket performs a minimal amount of internal configuration and waits for complete configuration by BIOS.

  • Page 74: Multi-Domain Commands

    Table 2-20. Multi-Domain Command Code Reference Domain 0 Domain 1 Command Name Code Code GetTemp() 0x01 0x02 RdPkgConfig() 0xa1 0xa2 WrPkgConfig() 0xa5 0xa6 RdIAMSR() 0xb1 0xb2 RdPCIConfig() 0x61 0x62 RdPCIConfigLocal() 0xe1 0xe2 WrPCIConfigLocal() 0xe5 0xe6 Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 75: Client Responses

    The Pass/Fail mask defined in Table 2-21 applies to all codes, and general response policies may be based on this information. Refer to Section 2.5.6 for originator response policies and recommendations. Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 76: Originator Responses

    GetTemp() response data. The output of this filter produces temperatures at the full 1/64°C resolution even though the DTS itself is not this accurate. Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 77 Table 2-24. Error Codes and Descriptions Error Code Description 0x8000 General Sensor Error (GSE) 0x8001 Reserved 0x8002 Sensor is operational, but has detected a temperature below its operational range (underflow) 0x8003-0x81ff Reserved § Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 78 Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 79: Technologies

    OS’s and applications without any special steps. • Enhanced: Intel VT enables VMMs to run 64-bit guest operating systems on IA x86 processors. • More reliable: Due to the hardware support, VMMs can now be smaller, less complex, and more efficient.

  • Page 80: Intel Vt-X Features

    3.1.3 Intel VT-d Objectives The key Intel VT-d objectives are domain-based isolation and hardware-based virtualization. A domain can be abstractly defined as an isolated environment in a platform to which a subset of host physical memory is allocated. Virtualization allows for the creation of one or more partitions on a single system.

  • Page 81: Intel Virtualization Technology Processor Extensions

    Intel TXT is a set of extensions designed to provide a measured and controlled launch of system software that will then establish a protected environment for itself and any additional software that it may execute.

  • Page 82: Intel Trusted Execution Technology - Server Extensions

    Intel® AES New Instructions (Intel® AES-NI), which is defined by FIPS Publication number 197. Since Intel AES-NI is the dominant block cipher, and it is deployed in various protocols, the new instructions will be valuable for a wide range of applications.

  • Page 83: Execute Disable Bit

    TDP limit. Note: Intel Turbo Boost Technology is only active if the operating system is requesting the P0 state. For more information on P-states and C-states refer to Section 4, “Power Management”.

  • Page 84: Enhanced Intel Speedstep® Technology

    3D modeling and analysis, scientific simulation, and financial analysts. Intel AVX is a comprehensive ISA extension of the Intel® 64 Architecture. The main elements of Intel AVX are: • Support for wider vector data (up to 256-bit) for floating-point computation.

  • Page 85: Intel Dynamic Power Technology

    — Application domain can scale out with advanced platform interconnect fabrics, such as Intel QPI. • Power Efficiency - Intel AVX is extremely power efficient. Incremental power is insignificant when the instructions are unused or scarcely used. Combined with the...
  • Page 86 Technologies Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 87: Power Management

    • PCIe/PCH and Remote Socket VccMin Snoops Freq = MinFreq • PCIe/PCH and Remote Socket PLL = ON Accesses PC2 - CC3-CC7 Snoopable Idle • Interrupt response time requirement • DMI Sidebands • Configuration Constraints Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 88: Integrated Memory Controller States

    • Register CKE Power Down: — IBT-ON mode: Both CKE’s are de-asserted, the Input Buffer Terminators (IBTs) are left “on”. — IBT-OFF mode: Both CKE’s are de-asserted, the Input Buffer Terminators (IBTs) are turned “off”. Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 89: Dmi2/Pci Express Link States

    Deep Power Down Down Power off Off, except RTC Suspend to RAM Power off Off, except RTC Suspend to Disk Power off Off, except RTC Soft Off Power off Power off Hard off Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 90: Processor Core/Package Power Management

    C-states have longer entry and exit latencies. 4.2.1 Enhanced Intel SpeedStep® Technology The following are the key features of Enhanced Intel SpeedStep Technology: • Multiple frequency and voltage points for optimal performance and power efficiency. These operating points are known as P-states.

  • Page 91: Requesting Low-Power Idle States

    However, software may make C-state requests using the legacy method of I/O reads from the ACPI-defined processor clock control registers, referred to as P_LVLx. This method of requesting C-states provides legacy support for operating systems that initiate C-state transitions via I/O reads. Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 92: Core C-States

    MWAIT C-state request. Therefore, P_LVLx reads do not directly result in I/O reads to the system. The feature, known as I/O MWAIT redirection, must be enabled in the BIOS. To enable it, refer to the Intel® 64 and IA-32 Architectures Software Developer’s Manual (SDM) Volumes 1, 2, and 3 .
  • Page 93 Power Management A System Management Interrupt (SMI) handler returns execution to either Normal state or the C1/C1E state. See the Intel® 64 and IA-32 Architectures Software Developer’s Manual (SDM) Volumes 1, 2, and 3 for more information. While a core is in C1/C1E state, it processes bus snoops and snoops from other threads.

  • Page 94: Package C-States

    The package C-states fall into two categories: independent and coordinated. C0/C1/ C1E are independent, while C2/C3/C6 are coordinated. Starting with the 2nd Generation Intel(r) Core(TM) Processor Family, package C-states are based on exit latency requirements which are accumulated from the PCIe* devices, PCH, and software sources.

  • Page 95: Package C-State Entry And Exit

    Autonomous power reduction actions which are based on idle timers, can trigger depending on the activity in the system. The package enters the C1 low power state when: Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 96 • L3 shared cache retains context and becomes inaccessible in this state. • Additional power savings actions, as allowed by the exit latency requirements, include putting Intel QPI and PCIe* links in L1, the uncore is not available, further voltage reduction can be taken.

  • Page 97: Package C-State Power Specifications

    Power Management • Additional power savings actions, as allowed by the exit latency requirements, include putting Intel QPI and PCIe* links in L1, the uncore is not available, further voltage reduction can be taken. In package C6 state, all cores have saved their architectural state and have had their core voltages reduced to zero volts.

  • Page 98: Cke Power-Down

    (1.5 V or 1.35 V) to the DDR IO must be maintained. 4.3.2.2 Self Refresh Exit Self refresh exit can be either a message from an external unit or as reaction for an incoming transaction. Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 99: Dram I/O Power Management

    (typically handled automatically when input receiver is disabled). DMI2/PCI Express* Power Management Active State Power Management (ASPM) support using L1 state, L0s is not supported. § Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 100 Power Management Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 101: Thermal Management Specifications

    This section provides data necessary for developing a complete thermal solution. For more information on designing a component level thermal solution, refer to the Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide .

  • Page 102: Tcase And Dts Based Thermal Specifications

    Some processor SKUs support two thermal profiles; refer to Table 5-1for a summary of the planned SKUs and their supported thermal profiles. Both ensure adherence to Intel reliability requirements. Thermal Profile 2U is representative of a volumetrically unconstrained thermal solution (that is, industry enabled 2U heatsink). With single thermal profile, it is expected that the Thermal Control Circuit (TCC) would be activated for very brief periods of time when running the most power intensive applications.
  • Page 103 DTS PECI commands will also support DTS temperature data readings. Please see Section 2.5.7, “DTS Temperature Data” for PECI command details. Also, refer to the Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for details on DTS based thermal solution design considerations.

  • Page 104: Processor Thermal Profiles

    80W (4-core) Figure 5-25 Figure 5-26 80W (2-core) Figure 5-25 Figure 5-27 Applies only to Intel® Xeon® Processor E5-4600 Product Family. 5.1.3.1 8-Core 150W Thermal Specifications Table 5-2. Tcase: 8-Core 150W Thermal Specifications, Workstation Platform SKU Only Core Thermal Design...

  • Page 105: Tcase: 8-Core 150W Thermal Profile, Workstation Platform Sku Only

    Table 5-3 for discrete points that constitute the thermal profile. Implementation of this Thermal Profile should result in virtually no TCC activation. Refer to the Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details.

  • Page 106: 8-Core 150W Thermal Profile, Workstation Platform Sku Only

    Table 5-3 for discrete points that constitute the thermal profile. Implementation of this Thermal Profile should result in virtually no TCC activation. Refer to the Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details.

  • Page 107: Tcase: 8-Core 135W Thermal Profile 2U

    Table 5-5 for discrete points that constitute the thermal profile. Implementation of this Thermal Profile should result in virtually no TCC activation. Refer to the Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details.

  • Page 108: Dts: 8-Core 135W Thermal Profile 2U

    Table 5-5 for discrete points that constitute the thermal profile. Implementation of this Thermal Profile should result in virtually no TCC activation. Refer to the Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details.

  • Page 109: Tcase: 8/6-Core 130W Thermal Specifications, Workstation/Server Platform

    Power specifications are defined at all VIDs found in Table 7-3. The processor may be delivered under multiple VIDs for each frequency. FMB, or Flexible Motherboard, guidelines provide a design target for meeting all planned processor frequency requirements. Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 110: Tcase: 8/6-Core 130W Thermal Profile 1U

    Notes: Please refer to Table 5-7 for discrete points that constitute this thermal profile. Refer to the Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details. Figure 5-6. DTS: 8-Core 130W Thermal Profile 1U...

  • Page 111: Dts: 6-Core 130W Thermal Profile 1U

    Please refer to Table 5-7 for discrete points that constitute the thermal profile. Refer to the Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details. Table 5-7. 8/6-Core 130W Thermal Profile Table 1U (Sheet 1 of 2) Maximum T (°C)

  • Page 112: Tcase: 6-Core 130W 1S Ws Thermal Profile

    7-3. The processor may be delivered under multiple VIDs for each frequency. FMB, or Flexible Motherboard, guidelines provide a design target for meeting all planned processor frequency requirements. Figure 5-8. Tcase: 6-Core 130W 1S WS Thermal Profile Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 113: Dts: 6-Core 130W 1S Ws Thermal Profile

    Table 5-9 for discrete points that constitute the thermal profile. Implementation of this Thermal Profile should result in virtually no TCC activation. Refer to the Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details.

  • Page 114: Tcase: 8-Core 115W Thermal Specifications 1U

    Power specifications are defined at all VIDs found in Table 7-3. The processor may be delivered under multiple VIDs for each frequency. FMB, or Flexible Motherboard, guidelines provide a design target for meeting all planned processor frequency requirements. Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 115: Tcase: 8-Core 115W Thermal Profile 1U

    Table 5-11 for discrete points that constitute the thermal profile. Implementation of this Thermal Profile should result in virtually no TCC activation. Refer to the Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details.

  • Page 116: Core 115W Thermal Profile Table 1U

    Thermal Management Specifications Refer to the Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details. Table 5-11. 8-Core 115W Thermal Profile Table 1U Power (W) Maximum T (°C) Maximum DTS (°C) CASE 55.0 55.0 56.1...

  • Page 117: Tcase: 8/6-Core 95W Thermal Profile 1U

    Please refer to Table 5-13 for discrete points that constitute this thermal profile. Refer to the Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details. Figure 5-13. DTS: 8-Core 95W Thermal Profile 1U Notes: Some processor units may be tested to lower TDP and the TEMPERATURE_TARGET MSR will be aligned to that lower TDP.

  • Page 118: Dts: 6-Core 95W Thermal Profile 1U

    Table 5-13 for discrete points that constitute this thermal profile. Refer to the Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details. Table 5-13. 8/6-Core 95W Thermal Profile Table 1U (Sheet 1 of 2) Maximum T (°C)

  • Page 119: Tcase: 8-Core 70W Thermal Profile 1U

    Table 5-15 for discrete points that constitute the thermal profile. Implementation of this Thermal Profile should result in virtually no TCC activation. Refer to the Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details.

  • Page 120: Dts: 8-Core 70W Thermal Profile 1U

    Table 5-15 for discrete points that constitute the thermal profile. Implementation of this Thermal Profile should result in virtually no TCC activation. Refer to the Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details.

  • Page 121: Tcase: 6-Core 60W Thermal Profile 1U

    Table 5-17 for discrete points that constitute the thermal profile. Implementation of this Thermal Profile should result in virtually no TCC activation. Refer to the Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details.

  • Page 122: Dts: 6-Core 60W Thermal Profile 1U

    Table 5-17 for discrete points that constitute the thermal profile. Implementation of this Thermal Profile should result in virtually no TCC activation. Refer to the Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details.

  • Page 123: Tcase: 4-Core 130W Thermal Profile 2U

    Table 5-19 for discrete points that constitute the thermal profile. Implementation of this Thermal Profile should result in virtually no TCC activation. Refer to the Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details.

  • Page 124: Dts: 4-Core 130W Thermal Profile 2U

    Table 5-19 for discrete points that constitute the thermal profile. Implementation of this Thermal Profile should result in virtually no TCC activation. Refer to the Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details.

  • Page 125: Tcase: 4-Core 130W 1S Ws Thermal Specifications, Workstation/Server Platform

    Power specifications are defined at all VIDs found in Table 7-3. The processor may be delivered under multiple VIDs for each frequency. FMB, or Flexible Motherboard, guidelines provide a design target for meeting all planned processor frequency requirements. Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 126: Tcase: 4-Core 130W 1S Ws Thermal Profile

    This Thermal Profile is representative of a volumetrically constrained platform. Please refer to Table 5-21 for discrete points that constitute this thermal profile. Refer to the Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details. Figure 5-22. DTS: 4-Core 130W 1S WS Thermal Profile...
  • Page 127 86.3 66.0 88.2 67.0 90.0 5.1.3.11 4-Core 95W Thermal Specifications The 4-Core 95W thermal specifications only applies to the Intel® Xeon® Processor E5- 4600 Product Family. Table 5-22. Tcase: 4-Core 95W Thermal Specifications 1U Core Thermal Design Minimum Maximum Notes...
  • Page 128 Table 5-23 for discrete points that constitute the thermal profile. Implementation of this Thermal Profile should result in virtually no TCC activation. Refer to the Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details.

  • Page 129: Tcase: 4/2-Core 80W Thermal Specifications 1U

    Table 5-23 for discrete points that constitute the thermal profile. Implementation of this Thermal Profile should result in virtually no TCC activation. Refer to the Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details.

  • Page 130: Tcase: 4/2-Core 80W Thermal Profile 1U

    Table 5-25 for discrete points that constitute the thermal profile. Implementation of this Thermal Profile should result in virtually no TCC activation. Refer to the Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details.

  • Page 131: Dts: 2-Core 80W Thermal Profile 1U

    Table 5-25 for discrete points that constitute the thermal profile. Implementation of this Thermal Profile should result in virtually no TCC activation. Refer to the Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details.

  • Page 132: Embedded Server Processor Thermal Profiles

    Power specifications are defined at all VIDs found in Table 7-3. The processor may be delivered under multiple VIDs for each frequency. FMB, or Flexible Motherboard, guidelines provide a design target for meeting all planned processor frequency requirements. Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 133: Tcase: 8-Core Lv95W Thermal Profile, Embedded Server Sku

    Table 5-28 for discrete points that constitute the thermal profile. Implementation of this Thermal Profile should result in virtually no TCC activation. Refer to the Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details.
  • Page 134 Table 5-28 for discrete points that constitute the thermal profile. Implementation of this Thermal Profile should result in virtually no TCC activation. Refer to the Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details.

  • Page 135: Tcase: 8-Core Lv70W Thermal Profile, Embedded Server Sku

    VIDs for each frequency. FMB, or Flexible Motherboard, guidelines provide a design target for meeting all planned processor frequency requirements. Figure 5-30. Tcase: 8-Core LV70W Thermal Profile, Embedded Server SKU Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 136: Core Lv70W Thermal Profile Table, Embedded Server Sku

    Table 5-30 for discrete points that constitute the thermal profile. Implementation of this Thermal Profile should result in virtually no TCC activation. Refer to the Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details.

  • Page 137: Thermal Metrology

    T temperature CASE measurements should be made. For detailed guidelines on temperature measurement methodology, refer to the Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide . Figure 5-32. Case Temperature (T ) Measurement Location CASE Notes: Figure is not to scale and is for reference only.

  • Page 138: Processor Core Thermal Features

    In addition, a thermal solution that is significantly under-designed may not be capable of cooling the processor even when the TCC is active continuously. Refer to the Intel® Xeon® Processor E5-1600/E5-2600/ E5-4600 Product Families Thermal/Mechanical Design Guide for information on designing a compliant thermal solution.

  • Page 139: Frequency And Voltage Ordering

    SVID/frequency points. Transition of the SVID code will occur first, to insure proper operation once the processor reaches its normal operating frequency. Refer to Figure 5-33 for an illustration of this ordering. Figure 5-33. Frequency and Voltage Ordering Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 140: On-Demand Mode

    (using Freq/SVID control). Clock modulation is not activated in this case. The TCC will remain active until the system de-asserts PROCHOT_N. Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 141: Thermtrip_N Signal

    5.2.6.1.1 Open Loop Thermal Throttling (OLTT) Pure energy based estimation for systems with no BMC or Intel ME. No memory temperature information is provided by the platform or DIMMs. The CPU is informed of the ambient temperature estimate by the BIOS or by a device via the PECI interface.
  • Page 142 PCU. When needed, system memory is then throttled using CAS bandwidth control. The processor supports dynamic reprogramming of the memory thermal limits based on system thermal state by the BMC or Intel ME. 5.2.6.3 MEM_HOT_C01_N and MEM_HOT_C23_N Signal The processor includes a pair of new bi-directional memory thermal status signals useful for manageability schemes.

  • Page 143: Signal Descriptions

    On Die Termination. Enables DRAM on die termination during Data Write or Data Read transactions. DDR{0/1/2/3}_PAR_ERR_N Parity Error detected by Registered DIMM (one for each channel). DDR{0/1/2/3}_RAS_N Row Address Strobe. DDR{0/1/2/3}_WE_N Write Enable. Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 144: Pci Express* Based Interface Signals

    Table 6-4. PCI Express* Port 2 Signals (Sheet 1 of 2) Signal Name Description PE2A_RX_DN[3:0] PCIe* Receive Data Input PE2A_RX_DP[3:0] PE2B_RX_DN[7:4] PCIe* Receive Data Input PE2B_RX_DP[7:4] PE2C_RX_DN[11:8] PCIe* Receive Data Input PE2C_RX_DP[11:8] Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 145: Pci Express* Port 3 Signals

    VSS. PCI Express* Hot-Plug SMBus Clock: Provides PCI Express* hot- plug support via a dedicated SMBus interface. Requires an external PEHPSCL general purpose input/output (GPIO) expansion device on the platform. Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 146: Dmi2/Pci Express* Port 0 Signals

    Signal Name Description QPI_RBIAS This input is used to control Intel QPI bias currents. QPI_RBIAS is required to be connected as if the link is being used even when Intel QPI is not used. Refer to the appropriate Platform Design Guide (PDG) for further details.

  • Page 147: Peci Signal

    TRST_N (Test Reset) resets the Test Access Port (TAP) logic. TRST_N must be driven TRST_N low during power on Reset. Note: Refer to the appropriate Platform Design Guide (PDG) for Debug Port implementation details. Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 148: Serial Vid Interface (Svid) Signals

    • 0: Service Processor Boot Mode Disabled. Example boot modes: Local PCH (this processor hosts a legacy PCH with firmware behind it), Intel QPI Link Boot (for processors one hop away from the FW agent), or Intel QPI Link Init (for processors more than one hop away from the firmware agent).
  • Page 149 SOCKET_ID[1:0] Socket ID Strap. Socket identification configuration straps for establishing the PECI address, Intel QPI Node ID, and other settings. This signal is used in combination with FRMAGENT to determine whether the socket is a legacy socket, bootable firmware agent is present, and DMI links are used in PCIe* mode (instead of DMI2 mode).

  • Page 150: Processor Power And Ground Supplies

    (sDP) platforms should choose this setting if the Node Controller does not support Intel TXT. 1 = Default. The platform is Intel TXT enabled. All sockets should be set to one. In a non- Scalable DP platform this is the default. When this is set, Intel TXT functionality requires user to explicitly enable Intel TXT via BIOS setup.
  • Page 151 Variable power supply for the processor system agent units. These include logic (non-I/O) for the integrated I/O controller, the integrated memory controller (iMC), the Intel QPI agent, and the Power Control Unit (PCU). The output voltage of this supply is selected by the processor, using the serial voltage ID (SVID) bus.
  • Page 152 Signal Descriptions Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 153: Electrical Specifications

    7.1.4 Intel QuickPath Interconnect (Intel QPI) The processor provides two Intel QPI port for high speed serial transfer between other processors. Each port consists of two uni-directional links (for transmit and receive). A differential signaling scheme is utilized, which consists of opposite-polarity (DP, DN) signal pairs.

  • Page 154: Platform Environmental Control Interface (Peci)

    The processor core, processor uncore, Intel® QuickPath Interconnect link, PCI Express* and DDR3 memory interface frequencies) are generated from BCLK{0/1}_DP and BCLK{0/1}_DN signals. There is no direct link between core frequency and Intel QuickPath Interconnect link frequency (for example, no core frequency to Intel QuickPath Interconnect multiplier).

  • Page 155: Jtag And Test Access Port (Tap) Signals

    Due to the voltage levels supported by other components in the JTAG and Test Access Port (TAP) logic, Intel recommends the processor be first in the TAP chain, followed by any other components within the system. Please refer to the Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families –...

  • Page 156: Decoupling Guidelines

    Vout MAX register (30h) is programmed by the processor to set the maximum supported VID code and if the programmed VID code is Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 157 The SetVID-slow command is preemptive, the VR interrupts its current processes and moves to the new VID. This is the instruction used for normal P-state voltage change. This command is used in the processor for the Intel Enhanced SpeedStep Technology transitions.

  • Page 158: Vr Power-State Transitions

    The processor must re-issue low power state (PS1 or PS2) command if it is in a low current condition at the new higher voltage. See Figure 7-2 for VR power state transitions. Figure 7-2. VR Power-State Transitions Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 159: Svid Address Usage

    1.45500 0.58500 0.76000 0.93500 1.11000 1.28500 1.46000 0.59000 0.76500 0.94000 1.11500 1.29000 1.46500 0.59500 0.77000 0.94500 1.12000 1.29500 1.47000 0.60000 0.77500 0.95000 1.12500 1.30000 1.47500 0.60500 0.78000 0.95500 1.13000 1.30500 1.48000 Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 160: Reserved Or Unused Signals

    Analog reference or output. May be used as a threshold voltage or for buffer compensation Asynchronous Signal has no timing relationship with any system reference clock. CMOS CMOS buffers: 1.05 V or 1.5 V tolerant Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 161 Direct Media Interface Gen 2 signals. These signals are compatible with PCI Express* 2.0 and 1.0 Signaling Environment AC Specifications. Intel QPI Current-mode 6.4 GT/s and 8.0 GT/s forwarded-clock Intel QuickPath Interconnect signaling Open Drain CMOS Open Drain CMOS (ODCMOS) buffers: 1.05 V tolerant PCI Express* PCI Express* interface signals.
  • Page 162 Analog Input/Output QPI_RBIAS Platform Environmental Control Interface (PECI) Single ended PECI PECI System Reference Clock (BCLK{0/1}) Differential CMOS1.05v Input BCLK{0/1}_D[N/P] SMBus Single ended Open Drain CMOS Input/ DDR_SCL_C{01/23} Output DDR_SDA_C{01/23} PEHPSCL PEHPSDA Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 163 VSS_VTTD_SENSE VTTD_SENSE VSA_SENSE VSS_VSA_SENSE Notes: Refer to Section 6, “Signal Descriptions” for signal description details. DDR{0/1/2/3} refers to DDR3 Channel 0, DDR3 Channel 1, DDR3 Channel 2 and DDR3 Channel 3. Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 164: Power-On Configuration (Poc) Options

    7.4. The signal used to latch PROCHOT_N for enabling FRB mode is RESET_N. BIST_ENABLE is sampled at RESET_N de-assertion and CPU_ONLY_RESET de-assertion (on the falling edge). This signal is sampled after PWRGOOD assertion. Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 165: Fault Resilient Booting (Frb)

    SVID SVIDCLK Mixing Processors Intel supports and validates and four two processor configurations only in which all processors operate with the same Intel QuickPath Interconnect frequency, core frequency, power segment, and have the same internal cache sizes. Mixing components operating at different internal clock frequencies is not supported and will not be validated by Intel.

  • Page 166: Flexible Motherboard Guidelines (Fmb)

    Electrical Specifications Technology transitions signal. Please refer to the Intel® 64 and IA-32 Architectures Software Developer’s Manual (SDM) Volumes 1, 2, and 3 for details on the FLEX_RATIO MSR and setting the processor core frequency. Not all operating systems can support dual processors with mixed frequencies. Mixing...

  • Page 167: Storage Conditions Specifications

    Provided as general guidance only, Intel board products are specified and certified to meet the following temperature and humidity limits (Non-Operating Temperature Limit: -40°C to 70°C & Humidity: 50% to 90%, non condensing with a maximum wet bulb of 28°C).

  • Page 168: Dc Specifications

    DC specifications are only valid while meeting specifications for case temperature specified in Section 5), clock frequency, and input voltages. Care should be CASE taken to read all notes associated with each specification. Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 169: Voltage And Current Specifications

    13. DC + AC + Ripple = Total Tolerance 14. For Power State Functions see Section 7.1.9.3.5. 15. V does not have a loadline, the output voltage is expected to be the VID value. SA_VID Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 170: Processor Current Specifications

    (T ) shown in Section 5, CASE “Thermal Management Specifications”. I is specified at the relative V point on the V load line. The processor is CC_MAX CC_MAX Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 171 1,2,3,4,5,6 VID - 0.129 VID - 0.144 VID - 0.159 1,2,3,4,5,6 VID - 0.133 VID - 0.148 VID - 0.163 1,2,3,4,5,6 Notes: The loadline specification includes both static and transient limits. Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 172 1,2,3,4,5,6 VID - 0.021 VID - 0.036 VID - 0.051 1,2,3,4,5,6 VID - 0.025 VID - 0.040 VID - 0.055 1,2,3,4,5,6 VID - 0.029 VID - 0.044 VID - 0.059 1,2,3,4,5,6 Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 173 The Adaptive Loadline Positioning slope is 0.8 m . The 4/2-core Icc ranges are as follows: • 0-150 A for 130 W processor 0-135 A for 95 W processo • • 0-100 A for 80 W processor Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 174 VID + 0.000 VID - 0.000 VID - 0.020 Maximum VID - 0.040 VID - 0.060 VID - 0.080 Typical VID - 0.100 VID - 0.120 Minimum VID - 0.140 VID - 0.160 Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 175: Die Voltage Validation

    VID). These specifications apply to the processor die voltage as measured across the VCC_SENSE and VSS_VCC_SENSE lands. Table 7-15. V Overshoot Specifications (Sheet 1 of 2) Symbol Parameter Units Figure Notes Magnitude of V overshoot above VID OS_MAX Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 176: Signal Dc Specifications

    0.57*V 2, 4, 5 DDR3 Data Buffer On Resistance Data ODT On-Die Termination for Data Signals PAR_ERR_N ODT On-Die Termination for Parity Error Signals Reference Clock Signals, Command, and Data Signals Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 177 11. DRAM_PWR_OK_C{01/23} must have a maximum of 30 ns rise or fall time over VCCD * 0.55 +300 mV and -200 mV and the edge must be monotonic. 12. The DDR01/23_RCOMP error tolerance is ± 15% from the compensated value. Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 178: Peci Dc Specifications

    The rising edge of BCLK{0/1}_DN is equal to the falling edge of BCLK{0/1}_DP. For Vin between 0 and Vih. Table 7-19. SMBus DC Specifications (Sheet 1 of 2) Symbol Parameter Units Notes Input Low Voltage 0.3*V Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 179: Jtag And Tap Signals Dc Specifications

    CPU I/O Voltage VTT - 3% 1.05 VTT + 3% Input Low Voltage 0.3*V Signals SVIDDATA, SVIDALERT_N Input High Voltage 0.7*V Signals SVIDDATA, SVIDALERT_N Output High Voltage TT(max) Signals SVIDCLK, SVIDDATA Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 180: Processor Asynchronous Sideband Dc Specifications

    Signals: CAT_ERR_N, ERROR_N[2:0], TT(max) THERMTRIP_N, PROCHOT_N, CPU_ONLY_RESET Output Leakage Current, ±100 Signal MEM_HOT_C{01/23}_N Output Leakage Current ±900 = 50 ohm) TEST Buffer On Resistance Signals: CAT_ERR_N, CPU_ONLY_RESET, ERROR_N[2:0], MEM_HOT_C{01/23}_N, PROCHOT_N, THERMTRIP_N Notes: Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 181: Miscellaneous Signals Dc Specifications

    7.8.3.3 Intel QuickPath Interconnect DC Specifications Intel QuickPath Interconnect specifications are defined at the processor lands. Please refer to the appropriate platform design guidelines for specific implementation details. In most cases, termination resistors are not required as these are integrated into the processor silicon.

  • Page 182: Bclk{0/1} Differential Clock Crosspoint Specification

    REFCLK + STABLE RB-Differential Figure 7-9. BCLK{0/1} Single Ended Clock Measurement Points for Absolute Cross Point and Swing = 1.40V BCLK_DN = 550mV CROSS MAX = 250mV CROSS MIN BCLK_DP = -0.30V Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 183: Signal Quality

    Signal Quality specifications for PCIe* Signals are included as part of the PCIe* DC specifications. Various scenarios have been simulated to generate a set of layout guidelines which are available in the appropriate Platform Design Guide (PDG). Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 184: Intel Quickpath Interconnect Signal Quality Specifications

    Intel QuickPath Interconnect Signal Quality Specifications Signal Quality specifications for Differential Intel® QuickPath Interconnect Signals are included as part of the Intel QuickPath Interconnect signal quality specifications. Various scenarios have been simulated to generate a set of layout guidelines which are available in the appropriate Platform Design Guide (PDG).

  • Page 185: Activity Factor

    However most systems will have multiple overshoot and/or undershoot events that each have their own set of parameters (duration, AF and magnitude). While each overshoot on its own may meet Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 186: Maximum Acceptable Overshoot/Undershoot Waveform

    0.2835 V 3 ns 5 ns 1.2600 V 0.210 V 5 ns 5 ns Figure 7-11. Maximum Acceptable Overshoot/Undershoot Waveform Over Shoot Over Shoot Duration Under Shoot Duration Under Shoot § Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 187: Processor Land Listing

    SSTL DDR0_BA[0] CM28 SSTL DDR0_DQ[05] SSTL DDR0_BA[1] CN27 SSTL DDR0_DQ[06] SSTL DDR0_BA[2] CM20 SSTL DDR0_DQ[07] SSTL DDR0_CAS_N CL29 SSTL DDR0_DQ[08] SSTL DDR0_CKE[0] CL19 SSTL DDR0_DQ[09] SSTL DDR0_CKE[1] CM18 SSTL DDR0_DQ[10] SSTL Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 188 DDR0_DQS_DP[07] CK40 SSTL DDR0_DQ[48] CB38 SSTL DDR0_DQS_DP[08] CC17 SSTL DDR0_DQ[49] CD38 SSTL DDR0_DQS_DP[09] SSTL DDR0_DQ[50] CE41 SSTL DDR0_DQS_DP[10] SSTL DDR0_DQ[51] CD42 SSTL DDR0_DQS_DP[11] CJ13 SSTL DDR0_DQ[52] CC37 SSTL DDR0_DQS_DP[12] CB10 SSTL Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 189 CC21 SSTL DDR1_DQ[08] SSTL DDR0_RAS_N CE29 SSTL DDR1_DQ[09] SSTL DDR0_WE_N CN29 SSTL DDR1_DQ[10] DC11 SSTL DDR01_RCOMP[0] CA17 Analog DDR1_DQ[11] DE11 SSTL DDR01_RCOMP[1] CC19 Analog DDR1_DQ[12] SSTL DDR01_RCOMP[2] CB20 Analog DDR1_DQ[13] SSTL Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 190 DDR1_DQS_DP[10] SSTL DDR1_DQ[51] CU41 SSTL DDR1_DQS_DP[11] SSTL DDR1_DQ[52] CT36 SSTL DDR1_DQS_DP[12] CT14 SSTL DDR1_DQ[53] CV36 SSTL DDR1_DQS_DP[13] CU31 SSTL DDR1_DQ[54] CT40 SSTL DDR1_DQS_DP[14] DC33 SSTL DDR1_DQ[55] CV40 SSTL DDR1_DQS_DP[15] CP38 SSTL Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 191 SSTL DDR2_DQ[13] AA41 SSTL DDR2_BA[0] SSTL DDR2_DQ[14] AF38 SSTL DDR2_BA[1] SSTL DDR2_DQ[15] AE37 SSTL DDR2_BA[2] SSTL DDR2_DQ[16] SSTL DDR2_CAS_N SSTL DDR2_DQ[17] SSTL DDR2_CKE[0] AA25 SSTL DDR2_DQ[18] SSTL DDR2_CKE[1] SSTL DDR2_DQ[19] SSTL Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 192 SSTL DDR2_DQS_DP[15] SSTL DDR2_DQ[56] SSTL DDR2_DQS_DP[16] SSTL DDR2_DQ[57] SSTL DDR2_DQS_DP[17] AC29 SSTL DDR2_DQ[58] SSTL DDR2_ECC[0] AF30 SSTL DDR2_DQ[59] SSTL DDR2_ECC[1] AF28 SSTL DDR2_DQ[60] SSTL DDR2_ECC[2] SSTL DDR2_DQ[61] SSTL DDR2_ECC[3] AB26 SSTL Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 193 SSTL DDR3_DQ[15] SSTL DDR3_BA[2] SSTL DDR3_DQ[16] SSTL DDR3_CAS_N SSTL DDR3_DQ[17] SSTL DDR3_CKE[0] SSTL DDR3_DQ[18] SSTL DDR3_CKE[1] SSTL DDR3_DQ[19] SSTL DDR3_CKE[2] SSTL DDR3_DQ[20] SSTL DDR3_CKE[3] SSTL DDR3_DQ[21] SSTL DDR3_CKE[4] SSTL DDR3_DQ[22] SSTL Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 194 SSTL DDR3_DQS_DP[17] SSTL DDR3_DQ[58] SSTL DDR3_ECC[0] SSTL DDR3_DQ[59] SSTL DDR3_ECC[1] SSTL DDR3_DQ[60] SSTL DDR3_ECC[2] SSTL DDR3_DQ[61] SSTL DDR3_ECC[3] SSTL DDR3_DQ[62] SSTL DDR3_ECC[4] SSTL DDR3_DQ[63] SSTL DDR3_ECC[5] SSTL DDR3_DQS_DN[00] SSTL DDR3_ECC[6] SSTL Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 195 PCIEX PE1B_RX_DN[6] PCIEX3 DMI_TX_DN[0] PCIEX PE1B_RX_DN[7] PCIEX3 DMI_TX_DN[1] PCIEX PE1B_RX_DP[4] PCIEX3 DMI_TX_DN[2] PCIEX PE1B_RX_DP[5] PCIEX3 DMI_TX_DN[3] PCIEX PE1B_RX_DP[6] PCIEX3 DMI_TX_DP[0] PCIEX PE1B_RX_DP[7] PCIEX3 DMI_TX_DP[1] PCIEX PE1B_TX_DN[4] PCIEX3 DMI_TX_DP[2] PCIEX PE1B_TX_DN[5] PCIEX3 Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 196 PCIEX3 PE2B_TX_DP[6] AN53 PCIEX3 PE3A_TX_DN[0] PCIEX3 PE2B_TX_DP[7] AP54 PCIEX3 PE3A_TX_DN[1] PCIEX3 PE2C_RX_DN[10] AL57 PCIEX3 PE3A_TX_DN[2] PCIEX3 PE2C_RX_DN[11] AU57 PCIEX3 PE3A_TX_DN[3] PCIEX3 PE2C_RX_DN[8] AK56 PCIEX3 PE3A_TX_DP[0] PCIEX3 PE2C_RX_DN[9] AM58 PCIEX3 PE3A_TX_DP[1] PCIEX3 Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 197 BP54 PE3D_RX_DN[14] AP46 PCIEX3 QPI0_DRX_DN[13] BN53 PE3D_RX_DN[15] AR45 PCIEX3 QPI0_DRX_DN[14] BP52 PE3D_RX_DP[12] AG47 PCIEX3 QPI0_DRX_DN[15] BR51 PE3D_RX_DP[13] AN47 PCIEX3 QPI0_DRX_DN[16] BP50 PE3D_RX_DP[14] AM46 PCIEX3 QPI0_DRX_DN[17] BJ49 PE3D_RX_DP[15] AN45 PCIEX3 QPI0_DRX_DN[18] BN49 Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 198 CA49 QPI1_DRX_DN[11] CR53 QPI0_DTX_DN[14] CG47 QPI1_DRX_DN[12] CT52 QPI0_DTX_DN[15] CF48 QPI1_DRX_DN[13] CL51 QPI0_DTX_DN[16] CF50 QPI1_DRX_DN[14] CK50 QPI0_DTX_DN[17] CF52 QPI1_DRX_DN[15] CL49 QPI0_DTX_DN[18] CG51 QPI1_DRX_DN[16] CM48 QPI0_DTX_DN[19] CG49 QPI1_DRX_DN[17] CN47 QPI0_DTX_DP[00] BV50 QPI1_DRX_DN[18] CM46 Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 199 DD46 RSVD BD48 QPI1_DTX_DN[14] CV44 RSVD BE43 QPI1_DTX_DN[15] DC45 RSVD BE45 QPI1_DTX_DN[16] DD44 RSVD BE47 QPI1_DTX_DN[17] CW43 RSVD BF46 QPI1_DTX_DN[18] DC43 RSVD BG43 QPI1_DTX_DN[19] DD42 RSVD BG45 QPI1_DTX_DP[00] CT48 RSVD BH44 Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 200 AG31 RSVD AG33 RSVD AG35 RSVD DA57 AG37 RSVD DB56 AG39 RSVD DC55 AG41 RSVD DD54 RSVD DE55 AL11 RSVD AL13 RSVD AL15 RSVD AL17 RSVD RSVD RSVD RSVD RSVD AM10 Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 201 AY10 AN13 AY12 AN15 AY14 AN17 AY16 AP10 AP12 BA11 AP14 BA13 AP16 BA15 BA17 AU11 BB10 AU13 BB12 AU15 BB14 AU17 BB16 AV10 AV12 BE11 AV14 BE13 AV16 BE15 BE17 Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 202 BP10 BG13 BP12 BG15 BP14 BG17 BP16 BH10 BH12 BR11 BH14 BR13 BH16 BR15 BR17 BJ11 BT10 BJ13 BT12 BJ15 BT14 BJ17 BT16 BK10 BK12 BU11 BK14 BU13 BK16 BU15 BU17 Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 203 VCCD_01 CP22 VCCPLL CA15 VCCD_01 CP24 AE15 VCCD_01 CP26 AE17 VCCD_01 CP28 AF18 VCCD_01 CW19 AG15 VCCD_01 CW21 AG17 VCCD_01 CW23 AH10 VCCD_01 CW25 AH12 VCCD_01 CW27 AH14 VCCD_01 DD18 AH16 Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 204 AF16 AF20 AF26 AF34 AF36 AF40 AF42 AF54 AF56 AA11 AA29 AA31 AG43 AA39 AG55 AA55 AG57 AB14 AH58 AB36 AJ15 AB42 AJ17 AK10 AC31 AK12 AK14 AD26 AK16 AD34 AD36 Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 205 BC17 AR11 AR13 BC43 AR15 BC45 AR17 BC53 BC55 BC57 AT10 AT12 BD10 AT14 BD12 AT16 BD14 BD16 AT46 AT52 BD54 BD56 AU45 AU47 BE49 AU49 BE51 AU51 BF42 AV42 BF44 Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 206 CA31 BM16 CA33 CA35 CA37 CA39 CA41 BN43 BN45 CA55 BP58 CA57 BR53 CB16 BR57 CB36 BT46 CB46 BT48 CB48 BT50 CB50 BT52 CB52 BT54 CB56 BT56 BU45 BU51 CC13 CC29 Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 207 CM40 CG33 CM42 CG35 CG37 CG39 CN11 CG41 CN13 CG43 CN15 CG53 CN17 CH12 CN31 CH16 CN33 CH36 CN35 CH44 CN37 CH46 CN39 CH48 CH50 CN53 CH52 CN55 CH54 CN57 CJ11 Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 208 DA43 CV14 DA45 CV18 DA47 CV30 CV32 DA51 CV34 CV38 DB12 CV42 CV54 DB32 CV58 DB36 DB58 CW11 CW13 DC41 CW15 CW29 DD10 CW31 DD12 CW33 DD14 CW35 DD34 CW37 DD36 Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 209 Land Name (Sheet 46 of 49) Land Name Land No. Buffer Type Direction Land Name Land No. Buffer Type Direction DD38 DE17 DE41 DE53 DF12 DF36 DF42 DF44 DF46 DF48 DF50 DF52 Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 210 AM54 VTTA AU53 VTTA CA53 VTTA CC45 VTTA CG55 VTTA CJ49 VTTA CR45 VTTA CR51 VTTA DA49 VTTA VTTA VTTD AF22 VTTD AF24 VTTD AG21 VTTD AG23 VTTD AM42 VTTD AT42 Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 211 Land No. Buffer Type Direction VTTD AY42 VTTD BD42 VTTD BH42 VTTD BK56 VTTD BL51 VTTD BM42 VTTD BR55 VTTD BU47 VTTD BV42 VTTD BY20 VTTD BY22 VTTD CA21 VTTD CA23 VTTD_SENSE BP42 Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 212: Listing By Land Number

    DDR2_DQS_DN[05] SSTL AA35 DDR2_DQ[28] SSTL AC11 DDR2_DQS_DN[04] SSTL AA37 DDR2_DQ[10] SSTL AC13 DDR2_DQ[32] SSTL AA39 AC15 DDR23_RCOMP[1] Analog AA41 DDR2_DQ[13] SSTL AC17 VCCD_23 AA43 PE3D_TX_DN[14] PCIEX3 AC19 VCCD_23 AA45 PE3D_TX_DP[12] PCIEX3 Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 213 PE2B_RX_DP[7] PCIEX3 AD32 DDR2_DQ[31] SSTL DDR2_DQ[47] SSTL AD34 AD36 AF10 DDR2_DQ[35] SSTL AD38 DDR2_DQS_DN[01] SSTL AF12 DDR2_DQS_DN[16] SSTL AF14 VSS_VSA_SENSE AD40 DDR2_DQ[09] SSTL AF16 AD42 AF18 AD44 DDR2_DQ[62] SSTL AD46 AF20 Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 214 PCIEX3 AJ45 PE3A_RX_DN[1] PCIEX3 AG31 AJ47 PE3D_RX_DN[12] PCIEX3 AG33 AJ49 PE3C_RX_DN[11] PCIEX3 AG35 AG37 AJ51 PE3C_RX_DN[9] PCIEX3 AG39 AJ53 PE2B_TX_DN[4] PCIEX3 AG41 AJ55 RSVD AG43 AJ57 PE2C_RX_DP[10] PCIEX3 AG45 PE3A_RX_DP[1] PCIEX3 Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 215 AL55 RSVD AL57 PE2C_RX_DN[10] PCIEX3 AP42 AP44 AM10 AP46 PE3D_RX_DN[14] PCIEX3 AM12 AP48 RSVD AM14 AP50 PE2A_TX_DN[1] PCIEX3 AM16 AP52 PE2A_TX_DN[3] PCIEX3 AP54 PE2B_TX_DP[7] PCIEX3 AP56 PE2D_RX_DP[13] PCIEX3 AM42 VTTD AP58 Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 216 AW15 AT56 PE2D_RX_DN[13] PCIEX3 AW17 AT58 PE2D_RX_DP[12] PCIEX3 AW43 BPM_N[5] ODCMOS AW45 BCLK1_DP CMOS AW47 PE2D_TX_DP[15] PCIEX3 AU11 AW49 PE2D_TX_DP[13] PCIEX3 AU13 AU15 AW51 PE2C_TX_DP[11] PCIEX3 AU17 AW53 PE2C_TX_DP[9] PCIEX3 AW55 Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 217 DDR3_DQ[23] SSTL BB52 DDR3_DQS_DN[11] SSTL BB54 PE2C_TX_DN[10] PCIEX3 BB56 PE2D_RX_DN[15] PCIEX3 DDR3_DQS_DN[00] SSTL BB58 DDR3_DQ[00] SSTL DMI_TX_DP[0] PCIEX DMI_TX_DP[2] PCIEX RSVD BC11 DMI_RX_DP[1] PCIEX BC13 DMI_RX_DP[3] PCIEX BC15 BC17 BC43 BC45 Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 218 BE13 BE15 BG51 QPI0_DRX_DP[00] BE17 BG53 QPI0_DRX_DN[02] BG55 QPI0_DRX_DN[03] BE43 RSVD BG57 QPI0_DRX_DN[08] BE45 RSVD BE47 RSVD BE49 BH10 BH12 BE51 BH14 BE53 QPI0_DRX_DP[02] BH16 BE55 QPI0_DRX_DP[03] BE57 QPI0_DRX_DP[08] BH42 VTTD Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 219 BK12 BM48 QPI0_DRX_DN[19] BK14 BM50 QPI0_DRX_DP[16] BK16 BM52 QPI0_DRX_DP[14] BM54 QPI0_DRX_DP[12] BM56 QPI0_DRX_DP[10] BK42 BM58 QPI0_CLKRX_DN BK44 RSVD BK46 BK48 BK50 BN11 BK52 BN13 BK54 BN15 BK56 VTTD BN17 BK58 QPI0_CLKRX_DP Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 220 BR11 BU49 SKTOCC_N BR13 BR15 BU51 BR17 BU53 QPI0_DTX_DP[02] BU55 QPI0_DTX_DP[04] BR43 RSVD BU57 QPI0_DTX_DP[07] BR45 SVIDDATA ODCMOS BR47 RSVD BR49 QPI0_DRX_DP[18] BV10 BV12 BR51 QPI0_DRX_DN[15] BV14 BR53 BV16 BR55 VTTD Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 221 BY14 VCCPLL DMI_TX_DP[3] PCIEX BY16 DDR_VREFDQRX_C01 DMI_RX_DP[0] PCIEX BY18 DMI_RX_DP[2] PCIEX VSS_VCC_SENSE BY20 VTTD PE1A_RX_DP[0] PCIEX3 BY22 VTTD RSVD BY24 BY26 DDR3_DQ[52] SSTL BY28 DDR3_DQ[34] SSTL BY30 DDR0_DQ[12] SSTL BY32 CA11 Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 222 CAT_ERR_N ODCMOS CB26 DDR0_CS_N[6] SSTL CC53 QPI_RBIAS_SENSE Analog CB28 DDR0_CS_N[3] SSTL CC55 QPI1_DRX_DP[00] CB30 DDR0_DQ[37] SSTL DDR0_DQ[00] SSTL CB32 DDR0_DQS_DN[13] SSTL CB34 DDR0_DQ[39] SSTL CD10 DDR0_DQS_DN[03] SSTL CB36 CD12 DDR0_DQ[27] SSTL Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 223 DDR0_DQ[32] SSTL DDR0_DQS_DN[09] SSTL CE33 DDR0_DQS_DN[04] SSTL CG11 RSVD CE35 DDR0_DQ[34] SSTL CG13 DDR0_DQ[20] SSTL CE37 DDR0_DQ[53] SSTL CG15 CE39 DDR0_DQS_DN[15] SSTL CG17 DDR0_ECC[6] SSTL CE41 DDR0_DQ[50] SSTL CG19 DDR0_MA[14] SSTL Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 224 CH38 DDR0_DQ[56] SSTL CK14 DDR0_DQS_DP[02] SSTL DDR0_DQ[10] SSTL CK16 DDR0_DQ[18] SSTL CH40 DDR0_DQS_DN[07] SSTL CK18 DDR0_ECC[7] SSTL CH42 DDR0_DQ[58] SSTL CK20 DDR0_MA[12] SSTL CH44 CK22 DDR0_MA[08] SSTL CH46 CK24 DDR0_MA[03] SSTL Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 225 CN17 CL41 DDR0_DQ[63] SSTL CN19 DDR0_MA[15] SSTL CL43 CN21 DDR0_MA[09] SSTL CL45 QPI1_DRX_DP[19] CN23 DDR0_MA[06] SSTL CL47 QPI1_DRX_DP[17] CN25 DDR0_CS_N[0] SSTL CL49 QPI1_DRX_DN[15] CN27 DDR0_BA[1] SSTL CN29 DDR0_WE_N SSTL CL51 QPI1_DRX_DN[13] Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 226 CT12 DDR1_DQ[28] SSTL CP42 CT14 DDR1_DQS_DP[12] SSTL CP44 CT16 DDR1_DQ[30] SSTL CP46 CT18 DDR1_CKE[5] SSTL CP48 DDR1_DQS_DP[09] SSTL CP50 CT20 DDR1_CKE[0] SSTL CP52 CT22 DDR1_ODT[0] SSTL CP54 RSVD CT24 DDR1_CS_N[5] SSTL Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 227 SSTL CV58 CU35 CU37 DDR1_DQ[49] SSTL DDR1_DQS_DN[02] SSTL CU39 DDR1_DQS_DP[06] SSTL TEST1 CU41 DDR1_DQ[51] SSTL CW11 CU43 QPI1_DTX_DP[17] CW13 CU45 QPI1_DTX_DP[11] CW15 CU47 QPI1_DTX_DP[05] CW17 DRAM_PWR_OK_C01 CMOS1.5v CU49 QPI1_DTX_DP[02] CW19 VCCD_01 Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 228 DDR1_DQ[45] SSTL CY34 DDR1_DQS_DN[05] SSTL DA11 CY36 DA13 DDR1_ECC[4] SSTL CY38 DDR1_DQS_DN[16] SSTL DA15 DDR1_ECC[6] SSTL DDR1_DQ[03] SSTL DA17 DDR1_CKE[3] SSTL CY40 DA19 DDR1_MA[09] SSTL CY42 DDR_SCL_C01 ODCMOS DA21 DDR1_CLK_DN[3] SSTL Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 229 DB32 DD12 DB34 DDR1_DQS_DP[05] SSTL DD14 DB36 DD16 DDR1_ECC[2] SSTL DB38 DDR1_DQS_DP[16] SSTL DD18 VCCD_01 TEST0 DD20 VCCD_01 DB40 DDR1_DQ[59] SSTL DD22 VCCD_01 DB42 QPI1_DTX_DP[19] DD24 VCCD_01 DB44 QPI1_DTX_DP[16] DD26 VCCD_01 Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 230 PCIEX DMI_RX_DN[0] PCIEX DDR1_DQS_DP[01] SSTL DMI_RX_DN[2] PCIEX DF10 DDR1_DQ[15] SSTL DF12 PE1A_RX_DN[0] PCIEX3 DF14 DDR1_ECC[1] SSTL RSVD DF16 DDR1_ECC[7] SSTL PE1A_RX_DP[3] PCIEX3 DF18 DDR1_BA[2] SSTL RSVD DF20 DDR1_MA[07] SSTL DDR3_DQ[48] SSTL Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 231 DDR3_DQ[15] SSTL VCCD_23 DDR3_CS_N[3] SSTL DDR3_DQ[61] SSTL DDR3_CS_N[5] SSTL DDR3_CS_N[0] SSTL PE1A_TX_DP[0] PCIEX3 DDR3_PAR_ERR_N SSTL PE1A_TX_DP[2] PCIEX3 DDR3_MA[09] SSTL PE1B_TX_DP[4] PCIEX3 PE1B_TX_DP[6] PCIEX3 DDR3_DQS_DN[08] SSTL PE3A_TX_DP[0] PCIEX3 DDR3_ECC[0] SSTL DDR3_DQ[56] SSTL Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 232 SSTL DDR3_DQ[28] SSTL DDR3_DQS_DP[14] SSTL DDR3_DQ[10] SSTL DDR3_DQ[44] SSTL DDR3_DQS_DN[01] SSTL DDR3_CS_N[9] SSTL DDR3_DQ[09] SSTL DDR3_CS_N[4] SSTL PE1A_TX_DN[1] PCIEX3 DDR3_CLK_DP[2] SSTL PE1A_TX_DN[3] PCIEX3 DDR3_CLK_DN[3] SSTL PE1B_TX_DN[5] PCIEX3 DDR3_CKE[0] SSTL PE1B_TX_DN[7] PCIEX3 Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 233 RSVD DDR3_DQS_DN[03] SSTL PE1B_RX_DN[5] PCIEX3 PE1B_RX_DN[7] PCIEX3 DDR2_DQ[21] SSTL DDR3_DQ[55] SSTL DDR2_DQ[02] SSTL DDR3_DQS_DP[05] SSTL DDR3_DQ[59] SSTL VCCD_23 DDR_VREFDQTX_C23 VCCD_23 PE3D_TX_DN[15] PCIEX3 VCCD_23 PE3C_TX_DP[8] PCIEX3 VCCD_23 PE3A_TX_DP[3] PCIEX3 VCCD_23 PE3B_TX_DP[6] PCIEX3 Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 234 SSTL DDR2_DQ[05] SSTL DDR2_DQ[52] SSTL DDR_SCL_C23 ODCMOS DDR2_CAS_N SSTL PE3C_TX_DN[10] PCIEX3 DDR2_MA[10] SSTL PE3A_TX_DN[2] PCIEX3 DDR2_MA[03] SSTL PE3B_TX_DN[7] PCIEX3 DDR2_MA[08] SSTL DDR2_MA[12] SSTL PE3B_TX_DN[5] PCIEX3 DDR2_CKE[1] SSTL PREQ_N CMOS PE2A_RX_DP[3] PCIEX3 Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 235 SSTL PE3D_TX_DP[13] PCIEX3 DDR2_ODT[1] SSTL PE3C_TX_DP[11] PCIEX3 DDR2_CLK_DN[2] SSTL RSVD DDR2_CLK_DN[3] SSTL PE3B_RX_DP[4] PCIEX3 DDR2_MA[14] SSTL PE3B_RX_DP[5] PCIEX3 DDR2_ECC[6] SSTL VTTA DDR2_DQ[18] SSTL DDR2_DQ[56] SSTL DDR2_DQ[41] SSTL DDR2_DQS_DN[02] SSTL DDR2_DQS_DP[14] SSTL Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 236 Processor Land Listing § Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 237: Package Mechanical Specifications

    Figure 9-1 shows a sketch of the processor package components and how they are assembled together. Refer to the Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for complete details on the LGA2011-0 land FCLGA10 socket.
  • Page 238 6. All drawing dimensions are in millimeters (mm). 7. Guidelines on potential IHS flatness variation with socket load plate actuation and installation of the cooling solution is available in the Intel® Xeon® Processor E5- 1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide .

  • Page 239: Processor Package Drawing Sheet 1 Of 2

    Package Mechanical Specifications Figure 9-2. Processor Package Drawing Sheet 1 of 2 Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 240: Processor Package Drawing Sheet 2 Of 2

    Package Mechanical Specifications Figure 9-3. Processor Package Drawing Sheet 2 of 2 Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 241: Processor Component Keep-Out Zones

    Dynamic loading is defined as an 11 ms duration average load superimposed on the static load requirement. See Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for minimum socket load to engage processor within socket. Package Handling Guidelines...

  • Page 242: Processor Mass Specification

    SUB - BRAND PROC # GRP1LINE3: SSPEC SPEED GRP1LINE4: XXXXX GRP1LINE5: {FPO } { e4} LOT NO S/N –0 Notes: XXXXX = Country of Origin SPEED Format = X.XX GHz and no rounding § Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 243: Boxed Processor Specifications

    2600 product family (LGA2011-0 land FCLGA10) processors will be offered as Intel boxed processors, however the thermal solutions will be sold separately. Boxed processors will not include a thermal solution in the box. Intel will offer boxed thermal solutions separately through the same distribution channels. Please reference Section 10.1.1...

  • Page 244: Intel Thermal Solution Sts200P And Sts200Pnrw (Boxed 25.5 Mm Tall Passive Heat Sink Solutions)

    PWM and PECI interface along with Digital Thermal Sensors (DTS). 10.1.3 Intel Thermal Solution STS200P and STS200PNRW (Boxed 25.5 mm Tall Passive Heat Sink Solutions) The STS200P and STS200PNRW are available for use with boxed processors that have TDP’s of 130W and lower.

  • Page 245: Mechanical Specifications

    None of the heat sink solutions exceed a mass of 550 grams. Note that this is per processor, a dual processor system will have up to 1100 grams total mass in the heat sinks. See Section 9.6 for details on the processor mass test. Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 246: Boxed Processor Motherboard Keepout Zones (1 Of 4)

    Boxed Processor Specifications Figure 10-4. Boxed Processor Motherboard Keepout Zones (1 of 4) Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 247: Boxed Processor Motherboard Keepout Zones (2 Of 4)

    Boxed Processor Specifications Figure 10-5. Boxed Processor Motherboard Keepout Zones (2 of 4) Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 248: Boxed Processor Motherboard Keepout Zones (3 Of 4)

    Boxed Processor Specifications Figure 10-6. Boxed Processor Motherboard Keepout Zones (3 of 4) Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 249: Boxed Processor Motherboard Keepout Zones (4 Of 4)

    Boxed Processor Specifications Figure 10-7. Boxed Processor Motherboard Keepout Zones (4 of 4) Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 250: Boxed Processor Heat Sink Volumetric (1 Of 2)

    Boxed Processor Specifications Figure 10-8. Boxed Processor Heat Sink Volumetric (1 of 2) Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 251: Boxed Processor Heat Sink Volumetric (2 Of 2)

    Boxed Processor Specifications Figure 10-9. Boxed Processor Heat Sink Volumetric (2 of 2) Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 252 Boxed Processor Specifications Figure 10-10.4-Pin Fan Cable Connector (For Active Heat Sink) Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 253 Boxed Processor Specifications Figure 10-11. 4-Pin Base Baseboard Fan Header (For Active Heat Sink) Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

  • Page 254: Boxed Processor Retention Mechanism And Heat Sink Support (Ilm-Rs)

    For specific design details on the standard and narrow ILM-RS and the Backplate please refer to the Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide .

  • Page 255: Boxed Processor Cooling Requirements

    These thermal solutions are for use with processor SKUs no higher than 130W (6 and 8 Core), or 80W (4 Core). Note: Please refer to the Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for detailed mechanical drawings of the STS200P and STS200PNRW.

  • Page 256: Boxed Processor Contents

    Table 10-2 Table 10-3 for detailed dimensions. Dimensions of heatsinks do not include socket or processor. 10.4 Boxed Processor Contents The Boxed Processor and Boxed Thermal Solution contents are outlined below. Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...
  • Page 257 Boxed Processor Specifications Boxed Processor • Intel® Xeon® processor E5-2600 product family • Installation and warranty manual • Intel Inside Logo Boxed Thermal Solution • Thermal solution assembly • Thermal interface material (pre-applied) • Installation and warranty manual § Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families...
  • Page 258 Boxed Processor Specifications Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One...

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