Hdlc Receive Buffer Descriptor (Rx Bd) - Motorola MC68302 User Manual

4.5.12.10 HDLC RECEIVE BUFFER DESCRIPTOR (Rx BO). The HDLC controller uses
the Rx BD to report information about the received data for each buffer. The
Rx BD is shown in Figure 4-12.
OFFSET+ 0
OFFSET+ 1
OFFSET+ 4
OFFSET+ 6
15 14 13 12 11 10
E J x J w J 1 J L l F J
J -
J - J - J LG
J
NO
J
AB
J
CR
J
av
I
co
DATA LENGTH
RX BUFFER POINTER
Figure 4-12. HDLC Receive Buffer Descriptor
The first word of the Rx BD contains control and status bits. Bits 15-10 are
written by the user before the buffer is linked to the Rx BD table, and bits
5-0 are set by the CP following frame reception. Bit 15 is set by the M68000
core when the buffer is available to the HDLC controller; it is cleared by the
HDLC controller when the buffer is full.
E- Empty
1 =The data buffer associated with the BD is empty. This bit signifies
that the BD and its associated buffer are available to the HDLC con-
troller. The M68000 core should not write to any fields of this BD
when this bit is set. The empty bit will remain set while the HDLC
controller is currently filling the buffer with received data.
0 =The data buffer associated with this BD has been filled with received
data, or data reception has been aborted due to an error condition.
The M68000 core is free to examine or write to any fields of the BD.
X - External Buffer
1 =The buffer associated with this BD is in external memory.
O=The buffer associated with this BD is in internal dual-port RAM.
W - Wrap (Final BD in Table)
1 =This is the last BD in the Rx BD table. After this buffer has been used,
the HDLC controller will receive incoming data into the first BD in the
table.
0 =This is not the last BD in the Rx BD table.
NOTE
The user is required to set the wrap bit in one of the first eight BDs;
otherwise, errant operation may occur.
MOTOROLA MC68302 USER'S MANUAL 4-61