Hdlc Programming Model; Hdlc Command Set - Motorola MC68302 User Manual

Integrated multi-protocol processor
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Table 4-4. HDLC-Specific Parameter RAM
Address
Name
Width
Description
SCC Base+9C
RCRC-L
Word
Temp Receive CRC Low
SCC Base+SE
RCRC-H
Word
Temp Receive CRC High
SCC Base+AO
*
C-MASl<-L
Word
Constant ($FOBS 16-Bit CRC, $DEBB 32-Bit CRC)
SCC Base+A2
*
C-MASl<-H
Word
Constant ($FOBS 16-Bit CRC, $20E3 32-Bit CRC)
SCC Base+A4
TCRC-L
Word
Temp Transmit CRC Low
SCC Base+A6
TCRC-H
Word
Temp Transmit CRC High
SCC Base+AS
DISFC
Word
Discard Frame Counter
SCC Base+AA
CRCEC
Word
CRC Error Counter
SCC Base+AC
ABTSC
Word
Abort Sequence Counter
SCC Base+AE
NMARC
Word
Nonmatching Address Received Counter
sec
Base+ BO
RETRC
Word
Frame Retransmission Counter
SCC Base+B2
*
MFLR
Word
Max Frame Length Register
SCC Base+B4
MAX-cnt
Word
Max..Length Counter
SCC Base+B6
*
HMASK
Word
User-Defined Frame Address Mask
SCC Base+ BB
*
HADDR1
Word
User-Defined Frame Address
SCC Base+ BA
*
HADDR2
Word
User-Defined Frame Address
SCC Base+ BC
*
HADDR3
Word
User-Defined Frame Address
SCC Base+ BE
*
HADDR4
Word
User-Defined Frame Address
*Initialized by the user (M6SOOO core).
4.5.12.4 HDLC PROGRAMMING MODEL. The M68000 core configures each SCC
to operate in one of four protocols by the MODE1-MODEO bits in the SCC
mode register (SCM). MODE1-MODE0=00 selects HDLC mode. The HDLC
controller uses the same data structure as the UART, BISYNC, and DDCMP
controllers. This data structure supports multibuffer operation and address
comparisons.
The receive errors (overrun, nonoctet aligned frame, CD lost, aborted frame,
and CRC error) are reported through the receive BO. The transmit errors
(underrun and CTS lost) are reported through the transmit BO. An indication
about the status of the lines (idle, CD, and CTS) is reported through the SCC
status register (SCCS), and a maskable interrupt is generated upon a status
change in any one of those lines.
4.5.12.5 HDLC COMMAND SET. The following commands are issued to the com-
mand register.
STOP TRANSMIT Command
After a hardware or software reset and the enabling of the channel in the
sec
mode register, the channel is in the transmit enable mode and starts
polling the first BO in the table.
MOTOROLA
MC68302 USER'S MANUAL
4-55

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