Inrq Interrupt Source Priorities - Motorola MC68302 User Manual

Integrated multi-protocol processor
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Table 3·2. EXRQ and INRQ Prioritization
Priority
Normal Mode
Dedicated Mode
Interrupt
Level
IPL2-IPLO
IRQ7, IRQ6, IRQ1
Source
7 (Highest)
000
IRQ7
EXRQ
6
001
IRQ6
EXRO
5
010
t
EXRQ
4
t
t
INRO
3
100
t
EXRQ
2
101
t
EXRQ
1 (Lowest)
110
IR01
EXRO
tPriority level not available to an external device in this mode.
3.2.2.2 INRQ INTERRUPT SOURCE PRIORITIES.
Although all INRQ interrupts are
presented at level 4, the interrupt controller further organizes interrupt ser-
vicing of the 15 INRQ interrupts according to the priorities illustrated in Table
3-3. The interrupt from the port B pin 3 (PB3) has the highest priority, and
the interrupt from the port B pin 0 (PBO) has the lowest priority. A single
interrupt priority within level 4 is associated with each table entry. The IOMA
entry is associated with the general-purpose OMA channel only, and not with
the SOMA channels that service the SCCs. Those interrupts are reported
through each individual SCC channel or, in the case of a bus error, through
the SOMA channels bus error entry.
Table 3-3. INRQ Prioritization within Interrupt Level 4
Priority
Level
Highest
Interrupt Source Description
General-Purpose Interrupt 3 (PB11)
General-Purpose Interrupt 2 (PB10)
SCC1
SDMA Channels Bus Error
IDMA Channel
SCC2
Timer 1
SCC3
General-Purpose Interrupt 1 (PB9)
Timer
2
SCP
Timer 3
SMC1
SMC2
General-Purpose Interrupt O (PB8)
Lowest
Error
MOTOROLA
MC68302 USER'S MANUAL
Multiple
Interrupt
Events
No
No
Yes
No
Yes
Yes
Yes
Yes
No
Yes
No
No
No
No
No
3-21

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