Motorola MC68302 User Manual page 167

Integrated multi-protocol processor
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4-64
the buffer and BD have been prepared and is cleared by the HDLC controller
after the frame has been transmitted.
R- Ready
1 =The data buffer, which has been prepared for transmission by the
user, has not yet transmitted. No fields of this BD may be written by
the user once this bit is set.
0 =This buffer is not currently ready for transmission. The user is free
to manipulate this BD (or its associated buffer). The HDLC controller
clears this bit after the buffer has been fully transmitted or after an
error condition has been encountered.
X - External Buffer
1 =The buffer associated with this BD is in external memory.
0 =The buffer associated with this BO is in internal dual-port RAM.
W - Wrap (Final BD in Table)
1 =This is the last BD in the Tx BD table. After this buffer has been used,
the HDLC controller will transmit data from the first BD in the table.
O=This is not the last BD in the Tx BD table.
NOTE
The user is required to set the wrap bit in one of the first eight BDs;
otherwise, errant behavior may occur.
I - Interrupt
1 =The M68000 core will be interrupted when this buffer has been serv-
iced by the HDLC controller.
0 =No interrupt is generated after this buffer has been serviced.
L - Last
1 =This is the last buffer in the current frame.
0 =This is not the last buffer in the frame.
TC-Tx CRC
This bit is valid only when the last bit is set.
1 =Transmit the CRC sequence after the last data byte.
0 =Transmit only the idle/flag sequence after the last data byte.
Bits
9-2 -
Reserved for future use.
MC68302 USER'S MANUAL
MOTOROLA

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