Motorola MC68302 User Manual page 101

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The clock frequency selected for the processor during low-power operation
determines not only the power consumed but also the choice of recovery
method. Provided the low-power frequency is sufficient to maintain the
M68000 core status, the programmer may select a nondestructive return to
full frequency and full power. This method of return causes the system control
block to switch the processor to full frequency after an interrupt from a
peripheral. The processor will then handle the interrupt in the usual manner.
In the lowest power-reduction mode, the processor frequency can be reduced
to a minimum which is consistent with maintaining bus activity for other
system elements. In this mode, after an interrupt occurs (from one of the 16
possible internal sources), the system control block returns the processor to
full frequency, drives the M68000 core RESET for 16-32 clock cycles, and
gives the processor a poweron interrupt indication. This return to normal
frequency and power is the alternative method that is destructive to the
M68000 core status and is equivalent to switching the power onto the M68000
core for the first time. In this lowest power mode, the destructive recovery
option (LPREC) must be used because the M68000 core status information
is lost as soon as the mode is entered. The dual-port RAM and internal
peripherals, however, retain their states.
The low-power logic uses eight bits in the SCR.
LPCD4-LPCDO - Low-Power Clock Divider Selects
The low-power clock divider select bits (LPCD$-LPCDO) specify the divide
ratio of the low-power clock divider equal to LPCD4-LPCDO
+
1. The system
clock is divided by 2, then divided by the clock divider value (1 to 32). Thus,
a divide ratio of 2 to 64 (LPCD4-LPCDO 0 to 15) can be selected.
After a sytem reset, these bits default to zero.
LPEN - Low-Power Enable
0 =The low-power modes are disabled.
1 =The low-power modes are enabled.
After a system reset, this bit defaults to zero to disable the low-power
modes.
LPP16 - Low-Power Clock Prescale Divide by 16
0 =The low-power clock divider input clock is the main clock.
1 =The low-power clock divider input clock is the main clock divided by
16. Thus, a divide ratio of 32 to 1024 (LPCD4-LPCDO 0 to 15) can be
selected.
After a system reset, this bit defaults to zero.
MC68302 USER'S MANUAL MOTOROLA