Smc2 Receive Buffer Descriptor; Smc2 Transmit Buffer Descriptor - Motorola MC68302 User Manual

Integrated multi-protocol processor
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4.7.4.3 SMC2 RECEIVE BUFFER DESCRIPTOR. In the IDL mode, this BD is identical
to the SMC1 receive BD. In the GCI mode, SMC2 is used to control the C/I
channel.
15
14
I
E
I
RESERVED
C/I
I
o
o
I
E- Empty
1 =This bit is set by the M68000 core to indicate that the data bits as-
sociated with this BD have been read.
O =This bit is cleared by the CP to indicate that the data bits associated
with this BD are now available to the M68000 core.
NOTE
Additional data received will be discarded until the empty bit is set
by the M68000 core.
Bits 14-6-These bits are reserved and should be set to zero by the M68000
core.
C/I - Command/Indication Channel Data
Bits 1-0 - The CP always writes these bits with zeros.
4.7.4.4 SMC2 TRANSMIT BUFFER DESCRIPTOR. In the IDL mode, this BD is iden-
tical to the SMC1 transmit BD. In the GCI mode, SMC2 is used to control the
C/I channel.
15
14
I
R
I
RESERVED
C/I
o
I
a
R- Ready
1 =This bit is set by the M68000 core to indicate that the data associated
with this BD is ready for transmission.
0 =This bit is cleared by the CP after transmission to indicate that the
BD is now available to the M68000 core.
Bits 14-6 - Reserved for future use; should be set to zero by the user.
C/I - Command/Indication Channel Data
Bits 1-0 - These bits should be written with zeros by the M68000 core.
MOTOROLA
MC68302 USER'S MANUAL
4-119

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