Motorola MC68302 User Manual page 53

3-6
NOTE
An interrupt will only be generated if IDMA is enabled in the IMR.
REQG - Request Generation
The following decode shows the definitions for the REQG bits:
00 =Internal request at limited rate (limited burst bandwidth) set by burst
transfer (BT) bits
01 =Internal request at maximum rate (one burst)
10=External request burst transfer mode (DREQ level sensitive)
11 =External request cycle steal (DREQ edge sensitive)
SAPI - Source Address Pointer (SAP) Increment
0 =SAP is not incremented after each transfer.
1 =SAP is incremented by one or two after each transfer, according to
the source size (SSIZE) bits and the starting address.
DAPI - Destination Address Pointer (DAP) Increment
0= DAP is not incremented after each transfer.
1 = DAP is incremented by 1 or 2 after each transfer, according to the
destination size (DSIZE) bits and the starting address.
SSIZE - Source Size
The following decode shows the definitions for the SSIZE bits.
00 =Reserved
01 =Byte
10=Word
11 =Reserved
DSIZE - Destination Size
The following decode shows the definitions for the DSIZE bits.
00 =Reserved
01 =Byte
10=Word
11 =Reserved
BT - Burst Transfer
The BT bits control the maximum percentage of the master bus that the
IDMA module can use during 1024 clock cycles. The IDMA runs for a con-
secutive number of cycles up to its burst transfer percentage if bus clear
(BCLR) is not asserted and the BCR is greater than zero. The following
decode shows these percentages.
00 = IDMA gets up to 75% of the bus bandwidth.
01 = IDMA gets up to 50% of the bus bandwidth.
10 = IDMA gets up to 25% of the bus bandwidth.
11 = IDMA gets up to 12.5% of the bus bandwidth.
MC68302 USER'S MANUAL MOTOROLA