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In the BDs for each protocol, indications are given as to whether the status
of these signals has changed during the reception of a given buffer. Fur-
thermore, in the event registers for each protocol, a maskable interrupt bit
is provided to allow convenient detection of a change in signal status.
RESERVED
ID
CD
I
CTS
Bits 7-3 - Reserved for future use.
ID - Idle Status on the Receiver Line
This status is valid only in the HDLC and UART modes.
CD - Carrier Detect Status on the Channel Pin
This bit has the same polarity as the external pin.
CTS - Clear-to-Send Status on Channel Pin
This bit has the same polarity as the external pin.
When the CTS and CD lines are programmed to software control in the SCC
mode register, these lines do not affect the SCC and can be used for other
purposes such as a data set ready (DSR) or a data terminal ready (DTR) line.
4.5.8.4
BUS ERROR ON SOMA ACCESS.
When a bus error occurs on an access
by the SOMA channel, the CP generates a unique interrupt (see 3.2
INTER-
RUPT CONTROLLER).
The interrupt service routine should read the bus error
channel number from the parameter RAM at BASE+ 672 as follows:
4-30
0 - SCC1 Tx Channel
1 - SCC1 Rx Channel
2 - SCC2 Tx Channel
3 - SCC2 Rx Channel
4-
SCC3 Tx Channel
5 - SCC3 Rx Channel
Next, the pointer that caused the bus error can be determined by reading
the Rx or Tx internal data pointer from the parameter's memory map of the
particular
sec.
MC68302 USER'S MANUAL
MOTOROLA
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