Time Slot Register - Tsr; Transmit Slot Mask Registers - Tsmax And Tsmbx - Motorola DSP56156 Manual

TDE is cleared when the DSP writes to the Transmit Data Register or when the DSP
writes to the TSR to disable transmission of the next time slot. If TIE is set, a SSI Transmit
Data interrupt request will be issued when TDE is set. The interrupt vector will depend on
the state of the Transmitter Underrun TUE bit. TDE is set by the DSP, SSIx, and STOP
reset.
8.13.7 SSISR Receive Data Register Full (RDF) Bit 7
The SSI Receive Data Register Full flag is set when the contents of the Receive Shift Reg-
ister are transferred to the Receive Data Register. When set, RDF indicates that data
should be read from RX so that the next word can be received without an overrun error.
RDF is cleared when the DSP reads the Receive Data Register. If RIE is set, a DSP re-
ceive data interrupt request will be issued when RDF is set. The interrupt vector request
will depend on the state of the Receiver Overrun ROE bit. RDF is cleared by the DSP,
SSIx, and STOP reset.
8.14

TIME SLOT REGISTER - TSR

The Time Slot Register is used when the data is not to be transmitted (i.e., a blank time
slot) in the available transmit time slot. For the purposes of timing, the time slot register is
a write-only register that behaves like an alternative transmit data register except that
rather than transmitting data, the transmit data pin, STD, is three-stated for that time slot.
8.15

TRANSMIT SLOT MASK REGISTERS - TSMAx AND TSMBx

The Transmit Slot Mask Registers are two 16-bit read/write registers. They are used by
the transmitter in network mode to determine for each slot whether to transmit a data word
and generate a transmitter empty condition (TDE=1), or to three-state the transmit data
pin, STD. TSMAx and TSMBx should be seen as only one 32-bit register, TSMx. Bit num-
ber N in TSMx is an enable/disable control bit for transmission in slot number N.
When bit number N in TSMx is cleared, the transmit data pin STD is three-stated during
transmit time slot number N. The data is still transferred from the Transmit Data Register
to the transmit shift register and the Transmitter Data Empty flag (TDE) is set. Also the
Transmitter Underrun Error flag is not set. This means that during a disabled slot, no
Transmitter Empty interrupt is generated (TDE=0). The DSP is interrupted by activity in
enabled slots only. Data that is written to the Transmit Data Register when servicing this
request is transmitted in the next enabled transmit time slot.
When bit number N in TSMx is set, the transmit sequence is as usual: data is transferred
from TX to the shift register, it is transmitted during transmit time slot number N, and the
TDE flag is set.
8 - 22 SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1)
TIME SLOT REGISTER - TSR
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