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Application:
P.L.L.
Input Divider
Divides Clock Frequency by 1 to 16
Feedback Divider
Multiplies Clock Frequency by 4 to 64; Increments of 4
Clockout Select
CS1 CS0
CLKOUT
0
0
PH0
0
1
Reserved
1
0
Squared F
1
1
Squared F
ext
GSM (Codec Clock Source)
0 = ÷Input Divider
1 = ÷6.5
PLL Power Down
0 = Off
1 = On
PLL Enable
0 = Disable
1 = Enable
VCO Lock – Read Only
0 = NOT Locked
1 = Locked
PLL Control Register (PLCR)
X:$FFDC Read/Write
Reset = $0000
MOTOROLA
DSP56156 Phase Locked Loop Programming Sheet
ext
∏π÷2
15 14 13 12 11 10
Lock PLLE
PLLD GSM
Figure C-6 PLL Control Register (PLCR)
PROGRAMMING SHEETS
Date:
Programmer:
9
8
7
6
*
*
CS1 CS0
YD3 YD2 YD1 YD0 ED3 ED2 ED1 ED0
0
0
= Reserved, Program as zero
*
Sheet 1 of 1
5
4
3
2
1
0
C - 21
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