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MODA/IRQA
Interrupt
MODB/IRQB
and Mode
MODC
Control
RESET
EXTAL
CLKO
Clock
SXFC
and
PLL
GNDS
A0-A15
D0-D15
Vdd Add/Data
Vss Add/Data
External
Bus
55 pins
(41 func.
5Vdd;9Vss)
PS/DS
Vdd Control
Vss Control
DSI/OS0
On-chip
DSCK/OS1
Emulation
Quiet Vdd
(Read/Write)- three state, active low output. Timing is the same as for the ad-
R/W
dress lines, providing an "early write" signal. R/W (which changes in t0) is high
for a read access and is low for a write access. If the external bus is not used
during an instruction cycle (t0,t1,t2,t3), R/W goes high in t0. R/W is three-stated
during hardware reset or when the DSP is not bus master.
MOTOROLA
BUS CONTROL (9 PINS)
VddS
DSP56156
4
8
BS
PORT A
WR
RD
R/W
TA)
BR
BG
BB
1
1
DSO
DR
2
112 pins
2
Vss
(86 functional pins
15 ground pins
9 power pins
1 Aground pins
1 Apower pin)
Figure 2-2 DSP56156 Pinout
DSP56156 PIN DESCRIPTIONS
PB0-PB7
H0-H7
PB8
HA0
PB9
HA1
PB10
HA2
PB11
HR/W
PB12
HEN
PB13
HREQ
PB14
HACK
1
Vdd Port B
1
Vss Port B
PC0
STD0
PC1
SRD0
PC2
SCK0
PC3
SC10
PC4
SC00
PC5
STD1
PC6
SRD1
PC7
SCK1
PC8
SC11
PC9
SC01
PC10
TIN
PC11
TOUT
Mic
Aux
SPKP
SPKM
Bias
Vref
Vdiv
1
VddA
1
VssA
1
Vdd port C
1
Vss Port C
Host
Parallel
Interface
Two
Serial
Interfaces
Timer
On-chip
Codec
2 - 5
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