Motorola DSP56156 Manual page 130

ON-CHIP CODEC FREQUENCY RESPONSE AND GAIN ANALYSIS
Table 6-8 Example of a Four Biquad IIR Decimation and Compensation Filter
; Source filter file: "adcomp128.IIR.Filter"
_filter_type
_NSTAGES
NOTE:
MOTOROLA
equ BIQUAD_FILTER_TYPE
equ 4
dc $02b2
; Biquad stage no. 1
dc $edc9
dc $16c4
dc $316a
dc $4186
; Biquad stage no. 2
dc $d708
dc $1721
dc $0d0c
dc $12dc
; Biquad stage no. 3
dc $f39a
dc $29f3
dc $3454
dc $4328
; Biquad stage no. 4
dc $c6af
dc $0b1d
dc $2ed3
dc $1b24
This filter, as well as all the figures representing filter re-
sponses, has been generated using ZOLA Technologies,
Inc., DSP Designer™ software package.
DSP56156 ON-CHIP SIGMA/DELTA CODEC
; number of stages
; gain = 0.04211689868/2
; -d2_1 = -0.284627003/2
; -d1_1 = 0.3557032662/2
; n2_1 = 0.7720730807/2
; n1_1 = 1.023796768/2
; -d2_2 = -0.6401634264/2
; -d1_2 = 0.3613604173/2
; n2_2 = 0.2038857781/2
; n1_2 = 0.2946510536/2
; -d2_3 = -0.1937047354/2
; -d1_3 = 0.6554721197/2
; n2_3 = 0.8176134701/2
; n1_3 = 1.049344022/2
; -d2_4 = -0.8955455145/2
; -d1_4 = 20.1736521771/2
; n2_4 = 0.7316442217/2
; n1_4 = 0.42404578/2
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