Motorola DSP56156 Manual page 232

Table 8-4 shows frame sync generation. When internally generated, both receive and
transmit frame sync are generated from the word clock and are defined by the frame rate
divider (DC4-DC0) bit and the word length (WL1-WL0) bits of CRA.
Figure 8-7 shows the functions of the two pins SC1x and SC0x according to the setting of
CRB flags.
8.4.1 Serial Transmit Data Pin - STDx
The Serial Transmit Data Pin (STD) is used for transmit data from the Serial Transmit Shift
Register. STD is an output when data is being transmitted and is three-stated between
data word transmissions and after the trailing edge of the bit clock after the last bit of a
word is transmitted.
8.4.2 Serial Receive Data Pin - SRDx
The Serial Receive Data Pin (SRD) is used to input serial data into the Receive Data Shift
Register.
8.4.3 Serial Clock - SCK
The Serial Clock (SCK) pin is used as a clock input or output used by both the transmitter
and receiver in synchronous modes and in asynchronous modes.
8.4.4 Serial Control - SC1x
The function of this pin is determined by the flags SYNC, FSD0 and FSD1 of control reg-
ister B (CRB) — see Table 8-4. In Asynchronous mode (SYNC=0), this pin is the receiver
frame sync I/O. For synchronous mode (SYNC=1), with bits FSD0 and FSD1 set, pin SCIx
is used as an output flag. When SC1x is configured as an output flag (FSD0=1; FSD0=1),
this pin is controlled by bit OF1 in CRB. When SCIx is configured as an input or output
(with synchronous or asynchronous operations), this pin will update status bit IF1 of the
SSI status register as described in Section 8.13.1.
MOTOROLA SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1)
SSIx DATA AND CONTROL PINS
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