Motorola DSP56156 Manual page 95

8 BIT
PARALLEL
INTERFACE
TO
HOST
PROCESSOR
HA0-HA2
HR/W
HEN
HACK
HREQ
5 - 4
INTRODUCTION
RXH
RXL
TXH
TXL
IVR
INTERRUPT
VECTOR
REGISTER
ICR
INTERRUPT
CONTROL
REGISTER
ISR
INTERRUPT
STATUS
REGISTER
CVR
COMMAND
VECTOR
REGISTER
INTERFACE
CONTROL
Figure 5-1 Host Interface Block Diagram
HOST INTERFACE
HTX
HRX
HF2,3
HCR
CONTROL
REGISTER
HSR
HF0,1
STATUS
REGISTER
HOST
INTERRUPTS
LOGIC
DSP GLOBAL
DATA BUS
MOTOROLA