Motorola DSP56156 Manual page 113

2. Overwriting Transmit Byte Registers.
The host programmer should not write to the transmit byte registers, TXH or TXL, un-
less the TXDE bit is set, indicating that the transmit byte registers are empty. This
guarantees that the DSP will read stable data when it reads the HRX register.
3. Synchronization of Status Bits from DSP to Host.
HC, HREQ, DMA, HF3, HF2, TRDY, TXDE, and RXDF status bits are set or cleared
from inside the DSP and read by the host processor. The host can read these status
bits very quickly without regard to the clock rate used by the DSP, but there is a chance
that the state of the bit could be changing during the read operation. This is generally
not a system problem, since the bit will be read correctly in the next pass of any host
polling routine. However, if the host holds the HEN input pin for the minimum assert
time plus 1.5 Ccyc, the Status data is guaranteed to be stable. The 1.5 Ccyc is first
used to synchronize the HEN signal and then to block internal updates of the status
bits. There is no other minimum HEN assert time relationship to DSP clocks. There is
a minimum HEN deassert time of 1.5 Ccyc so that the blocking latch can be deassert-
ed to allow updates if the host is in a tight polling loop. This only applies to reading
status bits.
The only potential system problem with the uncertainty of reading any status bits by
the host is HF3 and HF2 as an encoded pair. For example, if the DSP changes HF3
and HF2 from "00" to "11" there is a very small probability that the host could read the
bits during the transition and receive "01" or "10" instead of "11". If the combination of
HF3 and HF2 has significance, the host would potentially read the wrong combination.
Solutions:
a. Read the bits twice and check for consensus.
b. Assert HEN access for HEN + 1.5 Ccyc so that status bit transitions are stabilized.
4. Overwriting the Host Vector
The host programmer should change the Host Vector register only when the Host
Command bit (HC) is clear. This will guarantee that the DSP interrupt control logic will
receive a stable vector.
5. Cancelling a pending Host Command Exception
The host processor may elect to clear the HC bit to cancel the Host Command Excep-
tion request at any time before it is recognized by the DSP. Because the host does not
know exactly when the exception will be recognized, because of synchronization, and
because pipelining of exception processing, the DSP may execute the host exception
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HOST PORT USAGE – GENERAL CONSIDERATIONS
HOST INTERFACE MOTOROLA