Loop Counter (Lc) - Motorola DSP56156 Manual

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LF FV *
cessor at any given time. The CCR bits are affected by data ALU operations, one address
ALU operation (CHKAAU), bit field manipulation instructions, parallel move operations,
and by instructions which directly reference the CCR register. The CCR bits are not af-
fected by data transfers over XDB except if data limiting occurs when reading the A or B
accumulators or by the conditions described for the Sticky Bit, Bit 7. During processor re-
set, all CCR bits are cleared. The SR register is stacked when program looping is initial-
ized, when a jump or branch to subroutine (JScc, BScc, JSR, BSR) is performed, and
when long interrupts occur.
1.6.3.3

Loop Counter (LC)

The LC is a special 16-bit counter used to specify the number of times to repeat a hard-
ware program loop. This register is stacked by a DO instruction and unstacked by end of
loop processing or by execution of a BRKcc or an ENDDO instruction. When the end of a
hardware program loop is reached, the contents of the loop counter register are tested for
one. If the LC is one, the program loop is terminated and the LC register is loaded with
MOTOROLA
PROGRAMMING MODEL
MR
8 7
* S1 S0 I1 I0 S
Figure 1-11 Status Register Format
DSP56156 OVERVIEW
CCR
6 5 4 3 2 1 0
L E U N Z V C
Carry
Overflow
Zero
Negative
Unnormalized
Extension
Limit
Sticky Bit
Interrupt Mask
Scaling Mode
Reserved
Reserved
ForeVer Flag
Loop Flag
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