Ssi Clock And Frame Sync Generation; Ssix Data And Control Pins - Motorola DSP56156 Manual

8.3

SSI CLOCK AND FRAME SYNC GENERATION

Data clock and frame sync signals can be generated internally by the DSP or may be ob-
tained from external sources. If internally generated, the SSI clock generator is used to
derive bit clock and frame sync signals from the DSP internal system clock. The SSI clock
generator consists of a selectable fixed prescaler and a programmable prescaler for bit
rate clock generation and also a programmable frame rate divider and a word length di-
vider for frame rate sync signal generation.
8.4

SSIx DATA AND CONTROL PINS

The SSIx has five dedicated I/O pins for each SSI:
• Transmit data STDx (PC0 for SSI0 and PC5 for SSI1)
• Receive data SRDx (PC1 for SSI0 and PC6 for SSI1)
• Serial clock SCKx (PC2 for SSI0 and PC7 for SSI1)
• Serial Control Pin 1 SC1x (PC3 for SSI0 and PC8 for SSI1)
• Serial Control Pin 0 SC0x (PC4 for SSI0 and PC9 for SSI1)
Figure 8-1 through Figure 8-5 show the main configurations and the following paragraphs
describe the uses of these pins for each of the SSIx operating modes.These figures do
not represent all possible configurations, e.g., SCKx and FS don't have to be in the same
direction. Note that the first pin name in these figures apply to SSI0 and the second
applies to SSI1 i.e., PC2/PC7 means PC2 for SSI0 and PC7 for SSI1.
8 - 4 SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1)

SSI CLOCK AND FRAME SYNC GENERATION

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