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INTERFACE WITH THE DSP56156 CORE PROCESSOR
clears the CTDE bit in the codec status register COSR. The DSP may program the COIE
bit to cause a Codec Interrupt when CTDE is set.
6.4.5
Codec Control Register (COCR)
The Codec Control Register COCR is a 16-bit read/write register used to direct the on-
chip codec operation. The COCR bits are described in the following sections.
All COCR bits are cleared by DSP hardware and software reset.
6.4.5.1
COCR Audio Level Control Bits (VC3-VC0) Bits 0-3
Audio gain control is employed in the last stage of the on-chip codec D/A section. Bits
VC0-VC2 control the volume between -20 dB and 0 dB by 5 dB steps (see Table 6-2) and
VC3 is a boost bit which increases the volume level by 20 dB.
The digital reconstruction-interpolation filter performed by the DSP core can also be used
to control the output audio level in conjunction with the four VC3-VC0 bits. The gain of this
filter can be adjusted in order to modify the relative level and the step between levels. Ta-
ble 6-3 gives an example where the gain of the interpolation digital filter is adjusted in or-
der to provide an output volume control between -20 dB and +35 dB in 5 dB steps.
MOTOROLA
Table 6-2 Audio Level Control
VC3 VC2 VC1 VC0
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
DSP56156 ON-CHIP SIGMA/DELTA CODEC
Relative Level
in dB
0
-20
1
-15
0
-10
1
-5
0
0
1
6
0
12
1
18
0
0
1
6
0
12
1
18
0
24
1
30
0
30
1
35
6 - 7
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