Ivr Host Interface Interrupts; Dma Mode Operation - Motorola DSP56156 Manual

register is accessible only to the host processor. The contents of the IVR register are
placed on the Host Data Bus, H0-H7, when HREQ and HACK pins both are asserted and
the DMA mode is disabled. The content of this register is initialized to $0F by a DSP reset.
This corresponds to the un-initialized exception vector in the MC68000 family.
7 6 5
IV7 IV6 IV5
5.13

IVR HOST INTERFACE INTERRUPTS

The HI may request interrupt service from either the DSP or host processor. The DSP in-
terrupts are internal and do not require the use of an external interrupt pin. The DSP ac-
knowledges host interrupts by jumping to the appropriate interrupt service routine. The
DSP interrupt service routine must read or write the appropriate HI register (i.e. clearing
HRDF or HTDE for example) to clear the interrupt. In the case of Host Command inter-
rupts, the interrupt acknowledge from the program controller will clear the pending inter-
rupt condition.
The host processor interrupts are external and use the Host Request HREQ pin. HREQ
is normally connected to the host processor maskable interrupt (IRQ) input. The host pro-
cessor acknowledges host interrupts by executing an interrupt service routine. The
MC68000 processor family will assert the HACK pin to read the exception vector number
from the Interrupt Vector Register (IVR) of the HI. The most significant bit (HREQ) of the
Interrupt Status Register (ISR) may be tested to determine if the DSP is the interrupting
device and the two least significant bits (RXDF and TXDE) may be tested to determine
the interrupt source. The host processor interrupt service routine must read or write the
appropriate HI register to clear the interrupt.
5.14

DMA MODE OPERATION

The DMA mode allows the transfer of 8- or 16-bit data between the DSP HI and an exter-
nal DMA controller. The HI provides the pipeline data registers and the synchronization
logic between the two asynchronous processor systems. The DSP Host Exceptions pro-
vide cycle-stealing data transfers with the DSP internal or external memory. This allows
the DSP memory address to be generated using any of the DSP addressing modes and
modifiers. Queues and circular sample buffers are easily created for DMA transfer re-
gions. The DSP Host Exceptions appear as high priority fast or long exception service rou-
tines. The external DMA controller provides the transfers between the DSP HI registers
and the external DMA memory. The external DMA controller must provide the address to
the external DMA memory. The address of the selected HI register is provided by a DMA
address counter in the DSP HI.
5 - 18

IVR HOST INTERFACE INTERRUPTS

4 3 2
IV4 IV3 IV2 IV1
HOST INTERFACE
READ/WRITE
1 0
INTERRUPT CONTROL
REGISTER (IVR);
IV0
ADDRESS $3
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