Motorola DSP56156 Manual page 79

P:$C000, loading through the Host Interface, or loading through the Synchronous Serial
Interface SSI0.
When Mode 0 is selected, the external bus version of the bootstrap is executed. The data
contents of the external byte-wide memory must be organized as shown in Table 3-2.
Table 3-2 Data Mapping for External Bus Bootstrap
When Mode 1 is selected, the bootstrap is performed through the Host port or the SSI0
depending on the level of the most significant bit of P:$C000.
If Bit 15 of P:$C000 is zero (a pull-down resistor can be used in some applications), the
Host port bootstrap is selected. Typically a host processor will be connected to the 16-bit
DSP Host Interface and a host microprocessor will write the Host Interface Registers TXH
and TXL with the desired contents of PRAM from locations P:$0000 to P:$07FF. If less
than 2048 words are to be loaded into the PRAM, the host programmer can terminate the
bootstrap process by setting HF0=1 in the Host interface.
If bit 15 of P:$C000 is set (a pull-up resistor can be used in some applications), the boot-
strap is performed through the Synchronous Serial Interface SSI0. The bootstrap program
sets up the SSI0 in 8 bit mode, external clock, and asynchronous mode.
3 - 8 OPERATING MODES AND MEMORY SPACES
RAM MEMORY DESCRIPTION
Address of External
Byte-wide Memory
P:$C000
P:$C001
∗
∗
P:$CFFE
P:$CFFF
Contents Loaded
to Internal PRAM at:
P:$0000 low byte
P:$0000 high byte
∗
∗
P:$07FF low byte
P:$07FF high byte
MOTOROLA