Ssi Status Register (Ssisr) - Motorola DSP56156 Manual

8.12.14 CRB SSI Transmit Interrupt Enable (TIE) Bit 14
When the SSI Transmit Interrupt Enable bit is set, the program controller will be interrupt-
ed when the SSI Transmit Data Register Empty flag (TDE) in the SSI Status Register is
set. When TIE is cleared, this interrupt is disabled. However, the TDE bit will always indi-
cate the transmit data register empty condition even when the transmitter is disabled with
the TE bit. Writing data to the TX or TSR register will clear TDE thus clearing the interrupt.
There are two transmit data interrupts which have separate interrupt vectors:
1. Transmit data with exception status - This interrupt is generated on the follow-
ing condition:
TIE=1 and TDE=1 and TUE=1
2. Transmit data without exceptions - This interrupt is generated on the following
condition:
TIE=1 and TDE=1 and TUE=0
8.12.15 CRB SSI Receive Interrupt Enable (RIE) Bit 15
When the SSI Receive Interrupt Enable bit is set, the program controller will be interrupted
when the SSI Receive Data Register Full flag (RDF) in the SSI Status Register is set. If
RIE is cleared, this interrupt is disabled. However, the RDF bit still indicates the receive
data register full condition. Reading the receive data register will clear RDF and thus clear
the pending interrupt.
There are two receive data interrupts which have separate interrupt vectors:
1. Receive Data with exception status - This interrupt is generated on the following
condition:
RIE=1 and RDF=1 and ROE=1
2. Receive Data without exceptions - This interrupt is generated on the following
condition:
RIE=1 and RDF=1 and ROE=0
8.13

SSI STATUS REGISTER (SSISR)

The SSI Status Register is an 8-bit read only status register used by the DSP to interro-
gate the status and serial input flags of the SSI. The status bits are described in the fol-
lowing paragraphs.
MOTOROLA SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1)
SSI STATUS REGISTER (SSISR)
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