Introduction; General Description - Motorola DSP56156 Manual

6.1

INTRODUCTION

This section describes the DSP56156 Sigma/Delta ( Σ∆ ) over sampled voice band CO-
DEC block. It discusses the general block diagram of the A/D and D/A sections, the hand-
shake between the DSP56156 core processor and the codec, as well as the last decima-
tion antialiasing filter and first interpolation reconstruction filter performed in software by
the DSP56156 core processor.
6.2

GENERAL DESCRIPTION

The Σ∆ over sampled voice band CODEC block is built using HCMOS technology and uti-
lizes switched capacitor technology in some circuits. The CODEC contains one A/D con-
verter and one D/A converter. It also contains a reference voltage generator, a bias cur-
rent generator, and a master clock circuit (see Figure 6-1).
Vref
Figure 6-1 DSP56156 On-chip Sigma/Delta Functional Diagram
The A/D converter consists of an analog modulator with selectable input gain, a digital
low-pass comb filter, and a parallel bus interface. The analog modulator is a second-order
Σ∆ loop constructed of fully differential CMOS switched capacitor circuitry. The analog
modulator input is user selectable from one of two pins. The analog modulator output is
the input to a third-order digital comb filter which provides low-pass filtering and decima-
tion. The final 16-bit result is output through a parallel interface to the DSP56156 global
data bus.
MOTOROLA

INTRODUCTION

On-chip Codec Block
AFE
CLOCK
1:4
LPF COMB NS
DSP56156 ON-CHIP SIGMA/DELTA CODEC
DSP56156 Core Processor
decimation,
antialiasing
and
N:1
compensation
COMB DSP filter
program
1:N
interpolation,
COMB
reconstruction
and
compensation
DSP filters
program
DSP
program
6 - 3