Motorola DSP56156 Manual page 258

100KΩ
EXTAL
1000pF
CS1-CS0
÷
CLKO
2
On-chip Frequency Synthesis Control/Status Register
15 14
LOCK PLLE
7 6
YD3 YD2
Figure 9-1 Frequency Synthesis Block Diagram and Control Register
9.2 ON-CHIP CLOCK SYNTHESIS EXAMPLES
Three examples are given in Figure 9-2 in order to illustrate the functionality of the fre-
quency synthesis block.
9.2.1 Example One
In the first example, the 4-bit input divider is not used to provide the codec clock. Instead,
the 6.5 divider generates a 2 MHz clock to the codec from the 13 MHz external clock.
The input divider and the 4-bit PLL down counter can be used to select the desired oper-
ating frequency for the DSP core. The PLL output frequency cannot be lower than
10MHz and higher than the maximum DSP core operating frequency. The PLL can also
be disabled (PLLE=0), in which case the core will directly use the 13 MHz clock and will
run at 6.5 MIPS.
MOTOROLA
ON-CHIP CLOCK SYNTHESIS EXAMPLES
GSM=1
÷ 6.5
GSM=0
÷ 1 to ÷ 16
ED3-ED0
4-bit input divider
13 12 11
PLLD GSM CS1
5 4 3
YD1 YD0 ED3
ON-CHIP FREQUENCY SYNTHESIZER
XFC
SXFC
PHASE
Filter
COMP.
4-bit VCO down counter
÷ 1 to ÷ 16
YD3-YD0
10 9 8
CS0 ** **
2 1 0
ED2 ED1 ED0
0.01µF
0.1µF
VDDS GNDS
CODEC
PLLE=1
VCO
PLLE=0
÷4
internal phase PH0 at Fosc
READ-WRITE
PLL CONTROL
REGISTER (PLCR)
ADDRESS $FFDC
9 - 5
Fosc