Motorola DSP56156 Manual page 217

7 6 5
RDF TDE ROE
Note: All the flags in the SSISR are updated one SSI clock after the beginning of a time
slot.
8.13.1 SSISR Serial Input Flag 1 and 0 (IF0, IF1) Bit 0, 1
The SSI always latches data present on the SC1x and SC0x pins during reception of the
first received bit. IF0 and IF1 are always updated with this data when the receive shift reg-
ister is transferred into the receive data register. Hardware, software, SSI individual, and
STOP resets will clear IF0 and IF1.
8.13.2 SSISR Transmit Frame Sync (TFS) Bit 2
When set the Transmit Frame Sync flag (TFS) indicates that the first bit of the first active
word of the frame has been transmitted. Data written to the transmit data register when
TFS is set will be transmitted (in network mode) during the second active time slot in the
frame.
In network mode, TFS is set during transmission of the first active slot of the frame. It will
then be cleared when starting transmission of the next active slot of the frame. If the first
time slot of the frame is not enabled, this bit will be set on the leading edge of the first ac-
tive slot.
Note: In normal mode or in network mode with only one enabled slot, TFS will always
read as a one when transmitting data because there is only one time slot per frame.
TFS is cleared by DSP, SSIx or STOP reset and is not affected by TE.
8.13.3 SSISR Receive Frame Sync (RFS) Bit 3
When set, the Receive Frame Sync flag (RFS) indicates that reception of the word in the
Serial Receive Data Register (RX) occurred during the first active slot in the frame. When
RFS is cleared and a word is received, it indicates (only in the network mode) that the re-
ception of that word did not occur during the first active slot.
In network mode, if the first slot is disabled, this flag will be set after reception in the first
active slot and will only be cleared after receiving the next enabled time slot into the RX
register.
8 - 20 SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1)
SSI STATUS REGISTER (SSISR)
4 3 2
TUE RFS TFS
1 0
REGISTER (SR)
IF1 IF0
SSI0 ADDRESS $FFF0
SSI1 ADDRESS $FFF8
READ-ONLY
SSIx STATUS
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