Port B And Port C Registers - Motorola DSP56156 Manual

I/O PORT SET-UP AND PROGRAMMING
Bit 15 of the BCR, the Bus Request Hold bit, (RH), can be used for direct software control
of the BR pin. When this bit is set, the BR pin is asserted even though the DSP does not
need the bus. If RH is cleared, the BR pin will only be asserted if an external access is
being attempted or pending. RH is cleared by hardware reset.
Bit 14 of the BCR, the Bus State status bit (BS), is set if the DSP is currently bus master.
If the DSP is not the bus master, BS is cleared. In the slave mode, the BS bit is set when
the BG output pin is high and cleared when BG is low. In the master mode, BS is cleared
when the BG input pin is high and set when both pins (BG and BB) are low. This bit is set
by hardware reset
4.2.1.2

Port B and Port C registers

Port B consists of three read/write registers – a 1-bit Port B Control Register (PBC), a
15-bit Port B Data Direction Register (PBDDR), and a 15-bit Port B Data Register (PBD).
Port C consists of three read/write registers – a 12-bit Port C Control Register (PCC), an
12-bit Port C Data Direction Register (PCDDR), and a 12 bit Port C Data Register (PCD).
These registers are shown in Figure 4-2. All registers are read/write. Bit manipulation
instructions can be used to access individual bits.
4 - 6 I/O INTERFACE MOTOROLA