Data Alu - Motorola DSP56156 Manual

XAB2, or PAB. One instruction cycle is needed for each external memory access. There
is no speed penalty if only one external memory space is accessed in an instruction and
if no wait states are inserted in the external bus cycle. If two or three external memory
spaces are accessed in a single instruction, there will be a one or two instruction cycle
execution delay, respectively, or more if wait states are inserted on the external bus. A
bus arbitrator controls external accesses, making it transparent to the user. See the
DSP56100 Family Manual for additional information.
1.2.3

Data ALU

The Data ALU performs all arithmetic and logical operations on data operands and con-
sists of:
- four 16-bit input registers
- two 32-bit accumulator registers
- two 8-bit accumulator extension registers
- an accumulator shifter
- an output shifter
- one data bus shifter/limiter
- a parallel, single cycle, non-pipelined Multiply-Accumulator (MAC) unit
Data ALU registers may be read or written on the XDB and GDB as 16-bit operands (see
Figure 1-6). The Data ALU is capable of multiplication, multiply-accumulate with positive
or negative accumulation, addition, subtraction, shifting, and logical operations in one in-
struction cycle. Data ALU arithmetic operations generally use fractional two's complement
arithmetic. Some signed/unsigned and integer operations are also available. Data ALU
source operands may be 16, 32, or 40 bits and may originate from input registers and/or
accumulators. Data ALU results are always stored in one of the accumulators. The upper
16-bits of an accumulator can be used as a multiplier input. Arithmetic operations always
have a 40-bit result and logical operations are performed on 16-bit operands yielding 16-
bit results in one of the two accumulators.
The DSP56156 supports the two's complement representation of binary numbers. Un-
signed numbers are only supported by the multiply and multiply-accumulate instruction.
For fractional arithmetic, the 31-bit product is added to the 40-bit contents of either the A
or B accumulator. The 40-bit sum is stored back in the same accumulator. This multiply/
accumulate is a single cycle operation (no pipeline). Integer operations always generate
a 16-bit result located in the accumulator MSP (A1 or B1). Full precision integer opera-
tions are possible using the instructions IMPY or IMAC.
MOTOROLA
DSP56100 CORE BLOCK DIAGRAM DESCRIPTION
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