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RH BS *
*
15 14 13 12 11 10 9
*
*
*
*
15 14 13 12 11 10 9
* DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
14 13 12 11 10 9
15 14 13 12 11 10 9
* PB PB PB PB PB PB PB PB PB PB PB PB PB PB PB
14 13 12 11 10 9
15 14 13 12 11 10 9
*
*
*
* CC CC CC CC CC CC CC CC CC CC CC CC
11 10 9
15 14 13 12 11 10 9
*
*
*
* DC DC DC DC DC DC DC DC DC DC DC DC
11 10 9
15 14 13 12 11 10 9
*
*
*
* PC PC PC PC PC PC PC PC PC PC PC PC
11 10 9
15 14 13 12 11 10 9
* Reserved Bits; Read as zero and should be written as zero for future compatibility.
Figure 4-2 I/O Port B and C Programming Models
MOTOROLA
I/O PORT SET-UP AND PROGRAMMING
*
*
External X
Memory
8
7
6
5
*
*
*
*
*
*
*
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
I/O INTERFACE
PORT A
External P
BUS CONTROL
Memory
REGISTER (BCR)
X:$FFDE
4
3
2
1
0
PORT B
*
*
*
* BC
CONTROL
0
REGISTER (PBC)
X:$FFC0
4
3
2
1
0
PORT B
DATA DIRECTION
4
3
2
1
0
REGISTER (PBDDR)
X:$FFC2
4
3
2
1
0
PORT B
DATA
4
3
2
1
0
REGISTER (PBD)
X:$FFE2
4
3
2
1
0
PORT C
CONTROL
4
3
2
1
0
REGISTER (PCC)
X:$FFC1
4
3
2
1
0
PORT C
DATA DIRECTION
4
3
2
1
0
REGISTER (PCDDR)
X:$FFC3
4
3
2
1
0
PORT C
DATA
4
3
2
1
0
REGISTER (PCD)
X:$FFE3
4
3
2
1
0
4 - 7
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