Introduction; I/O Port Set-Up And Programming - Motorola DSP56156 Manual

4.1

INTRODUCTION

The DSP56156 provides 16 pins for an external address bus and 16 pins for an external
data bus. These pins are grouped to form the Port A bus interface. The DSP56156 also
provides 27 programmable I/O pins. These pins may be used as general purpose I/O pins
or allocated to an on-chip peripheral. Four on-chip peripherals are provided on the
DSP56156: an 8 bit parallel Host MPU/DMA digital interface, a 16-bit timer, and two Syn-
chronous Serial Interfaces (SSI0 and SSI1). These 27 pins are separate from the
DSP56156 address and data buses and are grouped as two I/O ports (B and C). Figure
4-1 shows the I/O block diagram.
Port B is a 15-bit I/O interface which may be used as general purpose I/O pins or as Host
MPU/DMA Interface pins. The Host MPU/DMA Interface provides a dedicated 8-bit paral-
lel port to a host microprocessor or DMA controller and can provide debugging facilities
via Host exceptions.
Port C is a 12-bit I/O interface which may be used as general purpose I/O pins or as Timer
and Serial Interface pins. The 16-bit timer can generate periodic interrupts based on a
multiple of the internal or external clock. The two Synchronous Serial Interfaces, SSI0 and
SSI1, are identical. They provide high speed synchronous serial data communication ca-
pability between the DSP56156 and other serial devices. Support for TDM network con-
figurations allows communication among up to 32 devices. Transparent linear-to-logarith-
mic companding and expanding is also supported for A-law and µ -law coded data.
These I/O interfaces are intended to minimize system chip count and "glue" logic in many
DSP applications. Each I/O interface has its own control, status, and data registers and is
treated as memory-mapped I/O by the DSP56156 (see Figure 4-2 and Figure 4-3). Each
interface has several dedicated interrupt vector addresses and control bits to enable/dis-
able interrupts. This minimizes the overhead associated with servicing the device since
each interrupt source may have its own service routine
4.2

I/O PORT SET-UP AND PROGRAMMING

Port A Bus Control Register (BCR), located at X:$FFDE, may be programmed to insert
wait states in a bus cycle during external data and program memory accesses. The BCR
is associated with Port A. Five bits are available in the control register for each type of
external memory access. Each 5 bit field can specify up to 31 wait states. On processor
reset, these five bits for both P and X memory are preset to all ones so that 31 wait states
are inserted allowing slow, inexpensive memory to be used. All other Port Control Regis-
ter bits are cleared on processor reset; i.e., reset sets the BCR to $03FF.
MOTOROLA
INTRODUCTION
I/O INTERFACE 4 - 3