Ssi Transmit Data Register (Tx); Ssi Receive Shift Register; Ssi Receive Data Register (Rx); Ssi Control Register A (Cra) - Motorola DSP56156 Manual

8.8

SSI TRANSMIT DATA REGISTER (TX)

The transmit data register is a 16-bit write-only register. Data to be transmitted is written
into this register and is automatically transferred to the transmit shift register when it be-
comes empty. The data written should occupy the most significant portion of the transmit
data register. The unused bits (least significant portion) of the transmit data register are
don't care bits. The DSP is interrupted whenever the transmit data register becomes emp-
ty provided that the transmit data register empty interrupt has been enabled. Tx is memory
mapped to X:$FFF1 for SSI0 and X:$FFF9 for SSI1.
Note: 1. When FSL=1, if the data is written into TX just between the frame sync and the
transmission of the first bit, the data will not be transmitted. TDE and TUE will
be set when the first bit is transmitted.
2. When the A/MU law is enabled, the data to be transmitted during the first en-
abled slot of a frame should be written to the TX register before the second to
last bit of the last slot of the previous frame. Otherwise a transmit underrun error
occurs.
8.9

SSI RECEIVE SHIFT REGISTER

This is a 16-bit shift register that receives the incoming data from the serial receive data
(SRD) pin. Data is shifted in by the selected (internal/external) bit clock when the associ-
ated frame sync input/output is asserted. Data is assumed to be received most significant
bit (MSB) first if the SHFD bit of CRB is cleared. If the SHFD bit is set, the data is assumed
to be received least significant bit first. Data is transferred to the SSI Receive Data Reg-
ister after 8, 12, or 16 bits have been shifted in depending on the Word Length control bits
(WL1-WL0) in SSI Control Register A. The receive shift register cannot be directly access-
ed by the programmer.
8.10

SSI RECEIVE DATA REGISTER (RX)

The SSI Receive Data Register is a 16-bit read-only register that accepts data from the
Receive Shift Register as it becomes full. The data read will occupy the most significant
portion of the receive data register. The unused bits (least significant portion) will read as
zeros. The DSP is interrupted whenever the receive data register becomes full if the as-
sociated interrupt is enabled. Rx is memory mapped to X:$FFF1 for SSI0 and X:$FFF9
for SSI1.
8.11

SSI CONTROL REGISTER A (CRA)

The SSI Control Register A is one of two 16-bit read/write control registers used to direct
the operation of the SSI. The CRA controls the SSI clock generator bit and frame sync
rates, word length, and number of words per frame for the serial data. The DSP reset
8 - 12 SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1)

SSI TRANSMIT DATA REGISTER (TX)

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