Icr Initialize Bit (Init) Bit 7 - Motorola DSP56156 Manual

next register. When the address counter reaches the highest register (RXL or TXL), the
address counter is not incremented but is loaded with the value in HM1 and HM0. This
allows 8- or 16-bit data to be transferred in a circular fashion and eliminates the need for
the DMA controller to supply the Host Address HA2, HA1 and HA0 pins. For 16-bit data
transfers, the DSP interrupt rate is reduced by a factor of 2 from the Host Request rate.
HM1 and HM0 are cleared by DSP reset.

5.10.7 ICR Initialize Bit (INIT) Bit 7

The INIT bit is used by the host to force initialization of the HI hardware. This may or may
not be necessary, depending on the software design of the interface. The type of initial-
ization done depends on the state of TREQ and RREQ. The INIT command is designed
to conveniently convert into the desired data transfer mode after the INIT is completed.
The commands are described below and in Table 5-5a. The host sets INIT which causes
the HI hardware to execute the command. The interface hardware clears INIT when the
command is complete. INIT is cleared by DSP reset.
Note that INIT execution always loads the DMA address counter and clears the channel
according to TREQ and RREQ. INIT execution is not affected by HM1 and HM0.
TREQ RREQ After INIT Execution — Interrupt Mode (HM1=0, HM0=0)
0
0
1
1
TREQ RREQ After INIT Execution
0
0
1
1
MOTOROLA
INTERRUPT CONTROL REGISTER (ICR)
Table 5-5a INIT Execution Definition
0 INIT=0; "address counter = 00"
1 INIT=0; RXDF=0; HTDE=1; "address counter = 00"
0 INIT=0; TXDE=1; HRDF=0; "address counter = 00"
1 INIT=0; RXDF=0; HTDE=1; TXDE=1; HRDF=0;
"address counter = 00"
Table 5-5ab INIT Execution Definition
0 INIT=0; address counter = HM1,HM0
1 INIT=0; RXDF=0; HTDE=1; address counter = HM1,HM0
0 INIT=0; TXDE=1; HRDF=0; address counter = HM1,HM0
1 Undefined (illegal)
HOST INTERFACE
— DMA Mode (HM1 or HM0 = 1)
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