5.15.2 Dsp Programmer Considerations - Motorola DSP56156 Manual

after the HC bit is cleared. For this reason, the HV must not be changed at the same
time the HC bit is cleared. In this way, if the exception was taken, the vector will be
known.

5.15.2 DSP programmer considerations

1. Reading HF1 and HF0 as an encoded pair.
DMA, HF1, HF0, HCP, HTDE, and HRDF status bits are set or cleared by the host pro-
cessor side of the interface. These bits are individually synchronized to the DSP clock.
The only system problem with reading status is HF1 and HF0 if they are encoded as
a pair, e.g. the four combinations 00, 01, 10, and 11 each have significance. This is
because there is a very small probability that the DSP will read the status bits that were
synchronized during transition. The solution to this potential problem is to read the bits
twice for consensus.
MOTOROLA
HOST PORT USAGE – GENERAL CONSIDERATIONS
HOST INTERFACE 5 - 23