Address Arithmetic; Linear Modifier; Reverse Carry Modifier - Motorola DSP56156 Manual

and one set for a second memory operation. Note that M3 is not used for updating R3 in
the second read in the X memory.
The special addressing modes include immediate and absolute modes as well as implied
references to the PC, system stack, and program memory. In addition, it is possible to use
the upper word (MSP) of an accumulator as an address.
1.7.4

Address Arithmetic

The DSP56156 Address Generation Unit supports linear, modulo, and bit-reversed ad-
dress arithmetic for all address register indirect modes. The address modifiers, Mn, deter-
mine the type of arithmetic used to update addresses. Address modifiers allow the
creation of data structures in memory for FIFOs (queues), delay lines, circular buffers,
stacks, and bit-reversed FFT buffers. Data is manipulated by updating address registers
(pointers) rather than moving large blocks of data. The contents of the address modifier
register, Mn, defines the type of address arithmetic to be performed for addressing mode
calculations, and for the case of modulo arithmetic, the contents of Mn also specifies the
modulus. Each address register Rn has its own modifier register Mn associated with it.
1.7.4.1

Linear Modifier

Address modification is performed using normal 16-bit (modulo 65,536) two's comple-
ment linear arithmetic. A 16-bit offset Nn, or immediate data (+1, -1, or a displacement
value) may be used in the address calculations. The range of values may be considered
as signed (Nn from -32,768 to +32,767) or unsigned (Nn from 0 to +65,536).
1.7.4.2

Reverse Carry Modifier

The address modification is performed by propagating the carry in the reverse direction,
i.e., from the MSB to the LSB. If the (Rn)+Nn addressing mode is used with this address
modifier, and Nn contains the value 2
equivalent to bit-reversing the K LSBs of Rn, incrementing Rn by 1, and bit-reversing the
K LSBs of Rn again. This address modification is useful for 2
range of values for Nn is 0 to +32,767 which allows bit-reversed addressing for FFTs up
to 65,536 points.
As an example, consider a 1024 point FFT with real and imaginary data stored in memory.
Then Nn would contain the value 512 and postincrementing by +N would generate the ad-
dress sequence 0, 512, 256, 768, 128, 640, ... This is the scrambled FFT data order for
sequential frequency points from 0 to 2π. For proper operation the reverse carry modifier
restricts the base address of the bit reversed data buffer to an integer multiple of 2
as 1024, 2048, 3072, etc. The use of addressing modes other than postincrement by Nn
is possible but may not provide a useful result.
1 - 36
INSTRUCTION SET SUMMARY
(a power of two), then postincrementing by Nn is
K-1
DSP56156 OVERVIEW
point FFT addressing. The
K
MOTOROLA
, such
K