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7.6
TIMER CONTROL REGISTER (TCR)
The timer control register is a 16-bit read/write register that contains the control bits for
the timer. The control bits are defined in the following paragraphs.
15 14 13 12 11 10
TE INV TO2 TO1 TO0 CIE OIE ES DC DC DC DC DC. DC DC DC
7.6.1
TCR Decrement Ratio (DC7-DC0) Bit 0-7
DC7-DC0 are 8 clock divider bits that are used to preset an 8-bit counter which is dec-
remented at the input clock rate. If DC7-DC0= n, n+1 clock cycles will be counted be-
fore decrementing the count register, i.e., the decrement register acts as a prescaler.
The 8-bit decrement register is not accessible to the user.
If the timer is disabled (TE=0) when a new value is written to this field, the decrement reg-
ister will start decrementing with this initial value when the timer gets enabled (TE=1). If
the timer is enabled (TE=1) when a new value is written to this field, the decrement reg-
ister will be reloaded with this value after it has reached the value zero. DC7-DC0 are set
to zero on hardware RESET and software reset (RESET instruction).
7.6.2
TCR Event Select (ES) Bit 8
The event select bit (ES) selects the source of the timer clock. If ES is cleared, Fosc/2 is
selected as input of the decrement register. If ES is set, an external signal coming from
the TIN pin is used as input to the decrement register. The external signal is synchronized
to the internal clock and should be lower than the maximum internal frequency Fosc/4. ES
is cleared by hardware RESET and software reset (RESET instruction).
7.6.3
TCR Overflow Interrupt Enable (OIE) Bit 9
The overflow interrupt has precedence over the compare interrupt at the same priority lev-
el. A compare interrupt will remain pending until all pending overflow interrupts are ser-
viced. When the Overflow Interrupt Enable bit (OIE) is set, the DSP will be interrupted at
the next event after the count register reaches zero. When the OIE bit is cleared, this in-
terrupt in disabled. OIE bit is cleared on hardware RESET and software reset (RESET in-
struction).
7 - 6
TIMER CONTROL REGISTER (TCR)
9
8
7
6
5
4
7
6
5
4
Figure 7-3 Timer Control Register
16-BIT TIMER AND EVENT COUNTER
3
2
1
0
TIMER CONTROL
REGISTER (TCR)
3
2
1
0
ADDRESS X:$FFEC
READ/WRITE
MOTOROLA
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