Icr Host Flag 1 (Hf1) Bit 4; Icr Host Mode Control (Hm1, Hm0) Bits 5 And 6 - Motorola DSP56156 Manual

5.10.5 ICR Host Flag 1 (HF1) Bit 4

The Host Flag 1 (HF1) bit is used as a general purpose flag for host processor to DSP
communication. HF1 may be set or cleared by the host processor and cannot be changed
by the DSP. Changing HF1 also changes the Host Flag bit 1 (HF1) of the Host Status reg-
ister HSR on the DSP side of the HI. HF1 is cleared by a DSP reset.

5.10.6 ICR Host Mode Control (HM1, HM0) Bits 5 and 6

The Host Mode control bits HM0 and HM1 select the transfer mode of the HI. HM1 and
HM0 enable the DMA mode of operation or interrupt (non-DMA) mode of operation.
When the DMA mode is enabled, the HREQ pin is used as a DMA Transfer Request out-
put to a DMA controller and the HACK pin is used as a DMA Transfer Acknowledge input
from a DMA controller. The DMA Control bits HM0 and HM1 select the size of the DMA
word to be transferred as shown in Table 5-4. The direction of the DMA transfer is select-
ed by the TREQ and RREQ bits.
Table 5-4 Host Mode (HM1, HM0) Bit Definition
When both HM1 and HM0 are cleared, the DMA mode is disabled and the TREQ and
RREQ control bits are used for host processor interrupting via the external Host Request
HREQ output pin. In the interrupt mode, the Host Acknowledge HACK input pin is used
for the MC68000 family vectored Interrupt Acknowledge input.
When HM1 or HM0 are set, the DMA mode is enabled and the HREQ pin is not available
for host processor interrupts. When the DMA mode is enabled, the TREQ and RREQ bits
selects the direction of DMA transfers; the Host Acknowledge HACK input pin is used as
a DMA Transfer Acknowledge input. If the DMA direction is from DSP to Host, the con-
tents of the selected register are enabled onto the Host Data Bus when HACK is asserted.
If the DMA direction is from Host to DSP, the selected register is written to TXH or TXL
from the Host Data Bus when HACK is asserted. The size of the DMA word to be trans-
ferred is determined by the DMA control bits HM0 and HM1. The HI register selected dur-
ing a DMA transfer is determined by a 2-bit address counter which is preloaded with the
value in HM1 and HM0. The address counter substitutes for the Host Address bits HA1
and HA0 of the HI during a DMA transfer. The Host Address bit HA2 is forced to one dur-
ing each DMA transfer. The address counter can be initialized with the INIT bit feature.
After each DMA transfer on the Host Data Bus, the address counter is incremented to the
5 - 14
INTERRUPT CONTROL REGISTER (ICR)
HM1 HM0 Mode
0 0 Interrupt Mode (DMA off)
0 1 Illegal
1 0 DMA mode - 16 bit
1 1 DMA mode - 8 bit
HOST INTERFACE MOTOROLA